Jason Ekstrand
234ecf26c6
anv/image: Add an aspects field
...
This makes several checks easier and allows us to avoid calling
anv_format_for_vk_format in a number of cases.
2016-05-17 12:17:22 -07:00
Grazvydas Ignotas
d14778656b
anv: fix warnings in release build
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Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings
in release build.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-04-25 12:23:31 +02:00
Jason Ekstrand
50018522d2
anv: s/anv_batch_emit_blk/anv_batch_emit/
...
Acked-by: Kristian Høgsberg <krh@bitplanet.net>
2016-04-20 14:54:09 -07:00
Jason Ekstrand
744e133431
anv/gen7_cmd_buffer: Use the new emit macro
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Acked-by: Kristian Høgsberg <krh@bitplanet.net>
2016-04-20 14:54:09 -07:00
Nanley Chery
79fbec30fc
anv: Remove default scissor and viewport concepts
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Users should never provide a scissor or viewport count of 0 because
they are required to set such state in a graphics pipeline. This
behavior was previously only used in Meta, which actually just
disables those hardware operations at pipeline creation time.
Kristian noticed that the current assignment of viewport count
reduces the number of viewport uploads, so it is not removed.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2016-04-13 18:02:38 -07:00
Jordan Justen
f60683b32a
anv: Invalidate state cache before L3 partitioning set-up.
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Port 10d84ba9f0
2016-03-28 17:01:35 -07:00
Jordan Justen
5879cb0251
anv: Fix cache pollution race during L3 partitioning set-up.
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Port 0aa4f99f56
2016-03-28 17:01:35 -07:00
Jordan Justen
8f3c236674
anv: Use genxml register support for L3 Cache config
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The programming of the L3 Cache registers should match the previous
manually packed LRI values.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-25 00:19:18 -07:00
Jordan Justen
1b126305de
anv/genX: Add flush_pipeline_select_gpgpu
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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-12 12:43:46 -08:00
Jason Ekstrand
248ab61740
anv/cmd_buffer: Pull the core of flush_state into genX_cmd_buffer
2016-03-08 17:10:05 -08:00
Jason Ekstrand
28cbc45b3c
anv/cmd_buffer: Split flush_state into two functions
2016-03-08 16:54:07 -08:00
Kristian Høgsberg Kristensen
2b29342fae
anv: Store prog data in pipeline cache stream
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We have to keep it there for the cache to work, so let's not have an
extra copy in struct anv_pipeline too.
2016-03-05 13:50:07 -08:00
Jason Ekstrand
f374765ce6
anv/cmd_buffer: Mask stencil reference values
2016-03-04 12:22:32 -08:00
Jason Ekstrand
ec18fef88d
anv/pipeline: Set StencilBufferWriteEnable from the pipeline
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The hardware docs say that StencilBufferWriteEnable should only be set if
StencilTestEnable is set. It seems reasonable to set them together.
2016-03-04 12:03:00 -08:00
Jason Ekstrand
fa8539dd6b
anv/pipeline: Respect pRasterizationState->depthBiasEnable
2016-03-04 12:03:00 -08:00
Jason Ekstrand
6e20c1e058
anv/cmd_buffer: Look at both sides for stencil enable
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Now it's all consistent with gen9
2016-03-01 11:03:29 -08:00
Jason Ekstrand
4cfdd16500
anv/cmd_buffer: Clean up stencil state setup on gen7
2016-03-01 11:02:21 -08:00
Jason Ekstrand
097564bb8e
anv/cmd_buffer: Dirty push constants when changing pipelines.
2016-02-29 14:36:24 -08:00
Jason Ekstrand
d29fd1c7cb
anv/cmd_buffer: Re-emit push constants packets for all stages
2016-02-29 14:36:24 -08:00
Jordan Justen
1af5dacd76
anv/gen7: Enable SLM in L3 cache control register
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Port 1983003
2016-02-28 11:54:49 -08:00
Jason Ekstrand
ad50896c87
anv/gen7: Only try to get the depth format the surface has depth
2016-02-27 11:23:18 -08:00
Jason Ekstrand
1f1cf6fcb0
anv: Get rid of GENX_FUNC
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It was a bad idea.
2016-02-20 09:12:38 -08:00
Jason Ekstrand
371b4a5b33
anv: Switch over to the macros in genxml
2016-02-20 09:09:28 -08:00
Jason Ekstrand
9851c8285f
Move the intel vulkan driver to src/intel/vulkan
2016-02-18 10:37:59 -08:00
