Commit graph

527 commits

Author SHA1 Message Date
Jordan Justen
8e735dc72c intel/isl: Add mocs settings for DG2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12712>
2021-10-08 00:48:10 +00:00
Jason Ekstrand
e7f3da0138 intel/isl: ASTC support was removed on Gfx12.5
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13206>
2021-10-06 15:04:33 +00:00
Jason Ekstrand
8afc9626ad intel/isl: Stop claiming ASTC works on Cherry View
We do, however, leave a nice tombstone comment in case anyone comes
looking.  Given the age and scarcity of Cherry View hardware and ASTC
apps that run on desktop Linux, it's unlikely we'll ever bother to
implement it.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13206>
2021-10-06 15:04:33 +00:00
Jason Ekstrand
0c618f308c intel/isl: Simplify isl_format_supports_filtering
For compressed formats, filtering and sampling has always gone together.
This lets us avoid duplicating all those nasty special cases between the
two functions.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13206>
2021-10-06 15:04:33 +00:00
Jason Ekstrand
231653ea35 intel/isl: Add a max_buffer_size limit to isl_device
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13199>
2021-10-06 02:18:39 +00:00
Jordan Justen
333b2185d8 intel/isl: Enable MOCS 61 for external surfaces on TGL
Reworks:
 * Lionel/Francisco: Add comment

Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by:  Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12292>
2021-09-14 05:33:53 +00:00
Nanley Chery
bd516c6581 intel/isl: Disable I915_FORMAT_MOD_Y_TILED on XeHP+
XeHP lacks support for Y-tiling.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
af40104e7d intel: Add underscores to HALIGN and VALIGN enums
The HALIGN enums for XeHP already have underscores. Make the other
HALIGN and VALIGN enums conform.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
3d1f6342c0 intel: Update surface states for XeHP alignments
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
fbde743b07 intel/isl: Use a switch for HALIGN/VALIGN encoding
Avoid using a sparse and relatively large array for HALIGN encoding.
Additionally, this provides validation of the input alignment values.

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
2e464e69b9 intel/isl: Fix halign/valign of uncompressed views
We're going to start asserting for valid halign/valign values during
surface state emission. Pre-SKL, isl_surf_get_uncompressed_surf creates
uncompressed surfaces with invalid halign/valign values - 1x1. Fix this
by replacing the call to isl_surf_get_image_surf with isl_surf_init,
passing in the uncompressed format up-front.

As we're no longer using isl_surf_get_image_surf, we also need to get
the x and y offset of the image ourselves. Instead of getting a
sample-based offset, then converting to elements later on, we use
isl_surf_get_image_offset_B_tile_el to get the offset in elements
up-front.

With the above two changes, the generic code after the else-block is no
longer needed for the single-layer-view code path. We move it and
specialize it to the if-block (which is executed SKL+ and handles
multi-layer views).

Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
79ad9cda48 intel: Support Tile4/64 in surface states
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
dd9ae2dc7b intel: Support Tile4/64 in depth/stencil state
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
f54de77c3a intel/isl: Update tiling filter functions for XeHP
Enable the XeHP-specific tilings and restrict them to that platform.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
0ab2fa18e4 intel/isl: Use an allow-list in gfx6_filter_tiling
Try to avoid having to update isl_gfx6_filter_tiling when new tilings
are added for new platforms. Note that the allow-list uses
ISL_TILING_ANY_Y_MASK and thus assumes that no new Y-tilings will be
added in the future.

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
602f597bc1 intel/isl: Drop ISL_SURF_USAGE_DISPLAY_*_BIT
We haven't used these since their introduction.

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
ac37d7801c intel/isl: Drop extra assert on array_pitch_el_rows
ISL already asserts that the variable is a multiple of the tile height
via isl_assert_div.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
4309012774 intel/isl: Size Tile64 surfaces with 4 dimensions
In order to size Tile64 surfaces correctly, make sure that the total
physical extent is arrayed. The code should handle 3D surfaces as well,
but is untested for now.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
8fd7678241 intel/isl: Update image alignments on XeHP
Implement the new XeHP alignment rules for surface layout.
RENDER_SURFACE_STATE objects still need updating, but that's left for a
separate commit.

Rework:
* Nanley: Include Sagar's VALIGN fix for D16_UNORM.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
0bcfa2d8fb intel/isl: Define ISL_TILING_4/64 for XeHP
XeHP defines new tiling formats, Tile4 and Tile64. They are needed in
order to support depth/stencil surfaces and multisampling. Create new
ISL enums and define some initial tiling information in order to enable
them later on.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
44ef425ce8 intel/isl: Add msaa_layout param to isl_tiling_get_info
The additional parameter will be used by Tile64.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Jason Ekstrand
e307d46eab intel/isl: Add more parameters to isl_tiling_get_info
They are not used yet but the layout of Yf and Ys tiles are dependent on
these parameters.  While we're here, better document the function.

Rework:
* Nanley: Update crocus.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
2021-08-25 22:39:30 +00:00
Nanley Chery
2ae70329f5 intel: Move the D16 workarounds out of ISL
Implement the workarounds in anv and iris instead.

Before this commit, ISL unconditionally modified workaround registers
while filling out depth stencil state. To account for this, drivers
unconditionally stalled prior to emitting depth stencil packets. This
hurt performance.

By having the drivers perform the workarounds, they can choose when to
modify the relevant registers. The drivers now avoid emitting the
workaround for NULL depth buffers. This reduces stalls and leads to
better performance.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (the ISL/Anv bits)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (the Iris bits)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>
2021-08-20 17:50:35 +00:00
Jason Ekstrand
782f75cb52 intel/isl: Use uint64_t for computed byte offsets
This is mostly a bit of future-proofing.  We never end up with offsets
that don't fit in 32 bits today because, thanks to driver limitations
caused by relocations, we don't allocate buffers bigger than 2GB today.
However, if we ever did, it's possible to create a surface on modern
platforms that consumes more than 4GB and we would end up with wrapping
in our offset calculations.

Acked-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11765>
2021-08-17 09:36:13 -05:00
Jason Ekstrand
eb7c28bf24 intel/isl: Add a missing assert in isl_tiling_get_intratile_offset_sa
Fixes: a4dafe1fad "intel/isl: Make the offset helpers four dimensional"
Acked-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11765>
2021-08-17 09:14:39 -05:00
Jason Ekstrand
7d521bc104 intel/isl: Better document isl_tiling_get_intratile_offset_*
The docs weren't updated when we switched it to 4D.  Also, the new docs
are way better.  While we're here, use the parameter name offset_B to be
more consistent.

Acked-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11765>
2021-08-17 09:14:39 -05:00
Jason Ekstrand
9ab2f7d489 intel/isl: Add units to view dimensions in isl_surf_get_uncompressed_surf
This makes things a bit more clear.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11765>
2021-08-17 09:14:39 -05:00
Jason Ekstrand
3702406154 intel/isl: Explicitly set offset_B = 0 in get_uncomp_surf for arrays
The only user of this case is iris which initializes offset_B to 0 so
there's no real bug here.  However, it is unexpected from an API PoV.

Fixes: 9946120d2b "intel/isl: Add more cases to isl_surf_get_uncompressed_surf"
Acked-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11765>
2021-08-17 09:14:39 -05:00
Eric Engestrom
4d9acfa533 python: drop explicit output_encoding='utf-8' in mako templates
Python 3 handles unicode strings by default, so we can drop all that.

Suggested-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3674>
2021-08-14 21:44:32 +00:00
Eric Engestrom
773a70f9cb isl: drop left-over comment
Fixes: cf9ff082b4 ("isl: Bring back isl_format_layout::bpb")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3674>
2021-08-14 21:44:32 +00:00
Eric Engestrom
e8937757ce isl: drop comment about "python 2 vs 3" as it doesn't apply anymore
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3674>
2021-08-14 21:44:32 +00:00
Eric Engestrom
f1eae2f8bb python: drop python2 support
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3674>
2021-08-14 21:44:32 +00:00
Ian Romanick
9dfe7fbc6b isl: Use CLAMP macro instead of MIN of MAX
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12177>
2021-08-03 12:55:11 -07:00
Ian Romanick
72259a870f util: Add and use functions to calculate min and max int for a size
Many places need to know the maximum or minimum possible value for a
given size integer... so everyone just open-codes their favorite
version.  There is some potential to hit either undefined or
implementation-defined behavior, so having one version that Just Works
seems beneficial.

v2: Fix copy-and-pasted bug (INT64_MAX instead of INT64_MIN) in
u_intmin.  Noticed by CI.  Lol.  Rename functions
`s/u_(uint|int)(min|max)/u_\1N_\2/g`.  Suggested by Jason.  Add some
unit tests that would have caught the copy-and-paste bug before wasting
CI time.  Change the implementation of u_intN_min to use the same
pattern as stdint.h.  This avoids the integer division.  Noticed by
Jason.

v3: Add changes to convert_clear_color
(src/gallium/drivers/iris/iris_clear.c).  Suggested by Nanley.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12177>
2021-08-03 12:55:02 -07:00
Lionel Landwerlin
8a99873712 isl: fix mapping of format->stringname
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ed6e586562 ("intel: properly constify isl_format_layouts")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5110
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12051>
2021-07-26 07:16:28 +00:00
Jason Ekstrand
9946120d2b intel/isl: Add more cases to isl_surf_get_uncompressed_surf
We can actually create array surfaces instead of requiring single-slice
in a few cases.  This does require us to be very careful about our
checks, though.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11647>
2021-07-06 19:29:42 +00:00
Jason Ekstrand
8f281be0ba intel/isl: Pull the uncompressed surface view code from anv
This adds a helper isl_surf_get_uncompressed_surf for creating a surface
which provides an uncompressed view into a compressed surface.  The code
is basically a direct port of the uncompressed surface code from the
Vulkan driver which, in turn, was a port from BLORP.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11647>
2021-07-06 19:29:42 +00:00
Jason Ekstrand
96ee78778b intel/isl: Add support for scratch buffers
XeHP adds support for a new surface type for scratch.  It's similar to
SURFTYPE_STRBUF in that it's a 2D array-of-struct format but the one
key difference is that the U coordinate is computed automatically based
on the thread ID and only the V coordinate is provided in the dataport
message.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
2021-06-25 00:18:29 +00:00
Jason Ekstrand
b8030ab1ea isl,docs: Add a chapter on AUX state tracking
We also update and improve the docs in isl.h which get pulled into this
new chapter.

Acked-by: Luis Strano <luis.strano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>
2021-06-24 13:57:40 +00:00
Jason Ekstrand
94a52bc85c isl,iris: Move the extra_aux_surf logic into iris
This gets rid of the awkward interface for isl_surf_get_ccs_surf where
we passed it two aux surfaces and it was supposed to fill out the second
one based on whether or not the first one already had stuff in it.
Instead, we now pass it three well-labled surfaces: surf,
hiz_or_mcs_surf, and ccs_surf which have obvious meanings.  This does
mean that iris has to carry a bit of logic and we have to flip
parameters around in all the callers.  But the resulting interface is
much cleaner.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>
2021-06-24 13:57:40 +00:00
Jason Ekstrand
37f76aab1c isl: Take a hiz_or_mcs_surf in isl_surf_supports_ccs
Whether or not a surface supports CCS on Tigerlake and later is
dependent not only on the main surface but also on the MCS or HiZ
surface, if any.  We were doing some of these checks in
isl_get_ccs_surf based on the extra_aux parameter but not as many as we
probably should.  In particular, we were really only checking HiZ
conditions and nothing for MCS.  It also meant that, in spite of the
symmetry in names, the checks in isl_surf_get_ccs_surf were more
complete than in isl_surf_supports_ccs.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>
2021-06-24 13:57:40 +00:00
Jason Ekstrand
2d2590a879 isl: Assert some iris invariants in isl_surf_get_ccs_surf
The only driver which calls isl_surf_get_ccs_surf with extra_aux != NULL
is iris and it always calls it with two aux surfaces and never calls it
for CCS twice.  We can turn those checks into asserts.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>
2021-06-24 13:57:40 +00:00
Jason Ekstrand
6b15ce9fa2 docs/isl: Add detailed documentation about tiling on Intel GPUs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
2021-06-18 13:03:48 +00:00
Jason Ekstrand
0f6ebd2b73 docs/isl: Add detailed documentation about isl formats
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
2021-06-18 13:03:48 +00:00
Jason Ekstrand
d07ec294bb isl: Document more members of isl_surf
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
2021-06-18 13:03:48 +00:00
Jason Ekstrand
00dc4e0d83 intel/isl: Use a 4D physical total extent for size calculations
With Yf and Ys tiling, everything is actually four dimensional because
we can have multiple depth or multisampled array slices in the same
tile.  This commit just enhances the calculations so they can handle it.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11330>
2021-06-11 20:51:21 +00:00
Jason Ekstrand
dc764916d9 intel/isl: Make tile logical extents four dimensional
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11330>
2021-06-11 20:51:21 +00:00
Jason Ekstrand
a4dafe1fad intel/isl: Make the offset helpers four dimensional
We need to do this in order to handle Yf and Ys tiling because they use
a four-dimensional tile instead of laying everything out in two
dimensions.

v2 (Jason Ekstrand):
 - Update functions added since v1:
    - isl_surf_get_image_range_B_tile
    - blorp_can_hiz_clear_depth
    - get_image_offset_el

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> (v1)
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11330>
2021-06-11 20:51:21 +00:00
Jason Ekstrand
0eb3d0a8df intel/isl: Add a isl_surf_get_image_offset_B_tile_el helper
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11330>
2021-06-11 20:51:21 +00:00
Dave Airlie
c04f20e7e0 intel/isl: add blend enable flag to gen4/5
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10655>
2021-06-08 12:35:52 +10:00