Commit graph

184721 commits

Author SHA1 Message Date
Jesse Natalie
8dd44c7e72 microsoft/compiler: Skip POS for io compaction
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31942>
2024-12-24 05:54:07 -05:00
Marek Olšák
dae57e184a glsl,st/mesa: always lower IO for GLSL, unlower IO for drivers
This enables nir_opt_varyings for all gallium drivers.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31942>
2024-12-24 05:54:07 -05:00
Marek Olšák
1dc85a34f3 st/mesa: add a pass that unlowers IO intrinsics to variables
We are going to switch all gallium drivers to nir_opt_varyings and then
use this to get IO variables in the end.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31942>
2024-12-24 05:54:07 -05:00
Qiang Yu
dff14d102d aco: fix voffset missing when buffer store base >=4096
Regression on test:
  dEQP-GLES31.functional.geometry_shading.basic.output_256

voffset is missing if buffer store base >=4096, we need to
re-calculate offen after resolve_excess_vmem_const_offset().

Fixes: cdaf269924 ("aco: inline store_vmem_mubuf/emit_single_mubuf_store")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32767>
2024-12-24 01:42:45 +00:00
Rohan Garg
5bddf6ceb0 iris: assert that we're not exporting a TILE64 surface
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32771>
2024-12-23 19:33:36 +00:00
Rohan Garg
308c2b9828 anv: refactor choose_isl_tiling_flags to pass fewer arguments
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32771>
2024-12-23 19:33:36 +00:00
Rohan Garg
f96b2c002d isl: disable aux when creating uncompressed TileY/Tile64 surfaces from compressed ones
Fixes: 8e96b51 ('intel/isl: Assert alignments of surface addresses')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32771>
2024-12-23 19:33:36 +00:00
Rohan Garg
abd137d079 iris: use CALLOC_STRUCT instead of calloc for readability
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32771>
2024-12-23 19:33:36 +00:00
Thomas H.P. Andersen
e38150f2fa drirc/nvk: force_vk_vendor=-1 for Artifact Classic
Without this the game crashes during the loading screen.

The game uses vkUpdateDescriptorSetWithTemplate and, in certain cases,
passes VkDescriptorBufferInfo structures where the offset + range
exceeds the size of the buffer. This triggers an assertion when
vk_buffer_range() is called, causing the game to crash.

When the nvidia vendor id is used the range is consistently set to 65536.
Without it the range varies and is much smaller - never exceeding 1000.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12349
Cc: stable
Reviewed-by: Faith Ekstrand <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32764>
2024-12-23 16:12:35 +00:00
Mary Guillemard
711b3351ef asahi: Remove unneeded dependencies for asahi_clc
There is no requirement on LLVM or SPIR-V tools since the introduction
of mesa-clc.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32719>
2024-12-23 15:09:41 +00:00
Mary Guillemard
5ddeea9a62 meson: Add precomp-compiler and install-precomp-compiler options
As Asahi, Intel and soon Panfrost requires an offline compiler for their
respective internal shaders, this commit adds generic new options to
workaround meson current limitations around cross-compillation.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32719>
2024-12-23 15:09:41 +00:00
Mary Guillemard
13fe5a597b meson: Add mesa-clc and install-mesa-clc options
Due to the cross build issues in current meson, we adds new options to
allow mesa_clc and vtn_bindgen to be installed or searched on the
system.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32719>
2024-12-23 15:09:40 +00:00
Juan A. Suarez Romero
4226be0c75 vc4: ensure sharing tiled resources are of proper format
When creating a tiled resource, it could be created either with "T" or
"LT" format.

But when sharing the resource, only "T" format is appropiate. So we need
to perform a conversion if required.

This is based on
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32661.

Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32703>
2024-12-23 13:08:43 +00:00
Mary Guillemard
631bea2e02 nak: Simplify 16-bit vector selection to not use try_from
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32679>
2024-12-23 11:47:49 +01:00
Mary Guillemard
979dfaf0bb nak: Fix 8-bit selection for vectors
This fix at least permutation issues on vec16 of 8-bits values for
cooperative matrix.

Fixes: 9e84e9e44b ("nak: Add base support for 8 and 16-bit types")
Suggested-by: M Henning <drawoc@darkrefraction.com>
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32679>
2024-12-23 11:47:32 +01:00
Samuel Pitoiset
2c323f2b8c radv: rename color output state to fragment output state
Now that it also exports depth.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32675>
2024-12-23 08:09:26 +00:00
Samuel Pitoiset
47dc9ca512 radv: rework emitting SPI_SHADER_Z_FORMAT
This fixes a small issue when the Z format in PS epilogs change, like
when alpha-to-coverage is enabled and then disabled.

igned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32675>
2024-12-23 08:09:26 +00:00
Daniel Schürmann
28a214728c ac/lower_ngg: move readlane into break blocks in streamout code generation for gfx12/ACO
This avoids unnecessary shuffle code and s_wait_loadcnt.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32743>
2024-12-21 12:32:25 +00:00
Daniel Schürmann
47227089d6 ac/lower_ngg: move break blocks after loop in streamout code generation for gfx12/ACO
By inverting the break condition, the loop becomes shorter.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32743>
2024-12-21 12:32:25 +00:00
Daniel Schürmann
39dcd9dedb ac/lower_ngg: Fix collecting buffer offsets from 4 lanes on gfx12
Also use readlane for improved performance.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32743>
2024-12-21 12:32:25 +00:00
David Rosca
ed58b869e1 frontends/va: Don't allow EndPicture without calling driver begin_frame
This can happen in decode context when application send no slice
buffers or in processing context with no processing buffers.
We need to avoid calling driver end_frame as no begin_frame will be
called in this case.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32677>
2024-12-21 09:34:01 +00:00
David Rosca
42e765d48b frontends/va: Don't allow Render/EndPicture without BeginPicture
It's not valid to call RenderPicture and EndPicture without calling
BeginPicture or when BeginPicture fails. FFmpeg will however call
EndPicture when BeginPicture fails, so we need to handle this.
Use target_id, which is assigned in BeginPicture, as an indication
whether we are inside the Begin - End picture sequence.

Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32677>
2024-12-21 09:34:01 +00:00
David Rosca
6e911cf252 frontends/va: Fix decoding VC1 interlaced video
VC1 has different start code for FRAME and FIELD, so we need to use
FIELD start code for second field.
Also simplify start code search to only look for 00 00 01.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2347
Cc: mesa-stable
Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32741>
2024-12-21 08:54:41 +00:00
Patrick Lerda
ad5c47502d r600: reverse fix spec ext_packed_depth_stencil getteximage
This change reverses d19e2597ce which is now superseded on the mesa
development branch by 42be38a8fb ("radeon/evergreen: ensure equal
sizes for depth-stencil npot textures").

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: David Heidelberg <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32553>
2024-12-21 05:07:16 +00:00
Alyssa Rosenzweig
83a7d9a814 hk: fix primitive restart dirty tracking
the previous logic was busted with the sequence Dolphin emits:

   BeginRender
   BindIndex
   Draw
   EndRender

   BeginRender
   Draw without restart
   Draw with restart
   EndRender

the second control stream would not have any restart index emitted, since the
dirty flag is set only on Begin and Bind, and cleared on draw.

this was probably also broken in the similar case

   BeginRender
   BindIndex
   Draw without restart
   Draw with restart
   EndRender

fixes Zelda: Wind Waker, Xeno Blade, etc.

thank you to pokechu22 for debug help!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:32 +00:00
Alyssa Rosenzweig
c585681378 hk: avoid compiling unneeded VS->GS variants
this should reduce pipeline compile time and memory bloat, now that we have no
non-XFB passthrough GS's.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:32 +00:00
Alyssa Rosenzweig
07e1b523b9 libagx: use designated initializers
these work now :-)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:32 +00:00
Alyssa Rosenzweig
a3b796ba19 libagx,hk: handle pipeline stats queries without a GS
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:32 +00:00
Alyssa Rosenzweig
5bc89aa991 hk,libagx: handle adjacency without a GS
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:32 +00:00
Alyssa Rosenzweig
872487919b hk,libagx: accelerate index buffer robustness
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:32 +00:00
Alyssa Rosenzweig
f106451a90 hk: factor out hk_draw_as_indexed_indirect
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:32 +00:00
Alyssa Rosenzweig
954080275b hk: use index buffer overflow check
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Alyssa Rosenzweig
e0cfc5eac1 libagx: factor out load/store_index
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Alyssa Rosenzweig
ff7abb1e22 libagx: refactor index buffer code
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Alyssa Rosenzweig
686daf2524 libagx: move index size helpers to the gpu
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Alyssa Rosenzweig
b5d41bc0fb agx: match another address pattern
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Alyssa Rosenzweig
7626e40506 asahi: reformat
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Alyssa Rosenzweig
fc4e533709 agx: add more 8-bit address fusing rules
helps kernel I'm writing

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Alyssa Rosenzweig
e110b8f2c9 libagx: add missing agx_vdm_return
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Alyssa Rosenzweig
b6dbfe822b asahi: use common draw
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Alyssa Rosenzweig
b9155de0a1 hk,libagx: move hk_draw to the gpu
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Asahi Lina
c80c56a315 asahi: hk: Enable timestamps for virt
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Asahi Lina
e281293508 asahi: Virt UABI update
Support timestamp extensions & fix a bunch of missing/broken things we
were dragging along.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Alyssa Rosenzweig
0d5db3238b asahi: fix mmap'ing imported BOs
bo->dev wasn't being set on the import path. apparently mmap'ing imported BOs is
really rare, so this slipped through. should address segfaults with gnome
settings.

Reported-by: girona
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Eric R. Smith
4533144608 panfrost: apply DEPTH_STENCIL flag consistently
We were inconsistent over the usage of PAN_BIND_DEPTH_STENCIL, putting
it on some stencil only formats but not others. Apply it to all
stencil formats. However, we also need to change is_format_supported
to ignore S8_UINT (at least for GLES), because the hardware is a little
weird with that format and the gallium driver gets confused by it.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32462>
2024-12-20 23:18:08 +00:00
Eric R. Smith
b6ade2714c panvk: fix fs_required()
If the sample mask is updated, we have to run the fragment
shader, so make sure this is reflected in fs_required()

Signed-off-by: Eric R. Smith <eric.smith@collabora.com>
Co-authored-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32462>
2024-12-20 23:18:08 +00:00
Caio Oliveira
5c0c3120ca intel/brw: Use variable instead of manually count the passes
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32709>
2024-12-20 22:41:20 +00:00
Caio Oliveira
ada898bb1c intel/brw: Disallow cmod in some cases of ARF scalar as destination
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32758>
2024-12-20 14:03:15 -08:00
Francisco Jerez
43d59c6186 intel/brw/xe3+: Relax SEND EOT register assignment restrictions.
These restrictions have been removed from the hardware.  Make the code
enforcing and validating them conditional.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32758>
2024-12-20 14:03:15 -08:00
nyanmisaka
8a5ec60442 frontends/vdpau: Get AV1 decode subsampling_x/y
The VDPAU frontend requires similar changes as in the VAAPI frontend.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12337

Signed-off-by: nyanmisaka <nst799610810@gmail.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32752>
2024-12-20 16:36:42 +00:00