Jordan Justen
1b79e7ebbd
i965: Store number of threads in brw_cs_prog_data
...
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-06-01 19:29:02 -07:00
Jordan Justen
8a80af2820
anv: Port L3 cache programming from i965
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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-17 13:04:03 -07:00
Jordan Justen
8ee31828c6
anv: Keep track of whether the data cache should be enabled in L3
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If images or shader buffers are used, we will enable the data cache in
the the L3 config.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-17 13:04:03 -07:00
Jason Ekstrand
50018522d2
anv: s/anv_batch_emit_blk/anv_batch_emit/
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Acked-by: Kristian Høgsberg <krh@bitplanet.net>
2016-04-20 14:54:09 -07:00
Jason Ekstrand
dba3727bea
anv/genX_pipeline: Use the new emit macro
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Acked-by: Kristian Høgsberg <krh@bitplanet.net>
2016-04-20 14:54:09 -07:00
Kristian Høgsberg Kristensen
2b29342fae
anv: Store prog data in pipeline cache stream
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We have to keep it there for the cache to work, so let's not have an
extra copy in struct anv_pipeline too.
2016-03-05 13:50:07 -08:00
Jordan Justen
635c0e92b7
anv: Set CURBEAllocationSize in MEDIA_VFE_STATE
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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-02-28 11:54:49 -08:00
Jason Ekstrand
371b4a5b33
anv: Switch over to the macros in genxml
2016-02-20 09:09:28 -08:00
Jason Ekstrand
e881c73975
anv/pipeline: Don't leak the binding map
2016-02-18 11:09:30 -08:00
Jason Ekstrand
9851c8285f
Move the intel vulkan driver to src/intel/vulkan
2016-02-18 10:37:59 -08:00
