Commit graph

39979 commits

Author SHA1 Message Date
Iago Toral Quiroga
7f0b4a803c gallium/ttn: VARYING_SLOT_PSIZ and VARYING_SLOT_FOGC are scalar
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-12 06:40:04 +00:00
Kenneth Graunke
6a82a374b4 iris: trivial whitespace fixes 2019-09-11 21:33:41 -07:00
Jonathan Marek
3690a53608 u_format: float type for R11G11B10_FLOAT/R9G9B9E5_FLOAT
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-09-11 22:39:19 -04:00
Jonathan Marek
8829f9ccb0 u_format: add ETC2 to util_format_srgb/util_format_linear
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-09-11 22:39:07 -04:00
Eric Anholt
272f9cfe6a dri: Use DRM_FORMAT_* instead of defining our own copy.
We have only two defines that aren't from DRM_FORMAT_*: SARGB and
SABGR.  Keep only those as __DRI_IMAGE_FOURCC and garbage collect the
rest.

While this header is also used from the X server, the X server doesn't
use any __DRI_IMAGE enums.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-09-11 13:05:10 -07:00
Anuj Phogat
729de1488f intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM
Initial benchmarking didn't show any performance benefits. But it might eventually.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-09-11 11:29:37 -07:00
Adam Jackson
96b592696f gallium: Require LLVM >= 3.9
To go any further than this would be to break the current version of
Android.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-09-11 17:00:43 +00:00
Adam Jackson
585d095610 gallium: Require LLVM >= 3.8
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-09-11 17:00:43 +00:00
Adam Jackson
59f18f2159 gallium: Require LLVM >= 3.7
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-09-11 17:00:43 +00:00
Adam Jackson
9abf7d5755 gallium: Require LLVM >= 3.6
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-09-11 17:00:43 +00:00
Adam Jackson
3c553d9cff gallium: Require LLVM >= 3.5
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

[ Michel Dänzer: Dropped jessie line from debian-install.sh again ]
2019-09-11 17:00:43 +00:00
Adam Jackson
4fdd455eeb gallium: Require LLVM >= 3.4
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-09-11 17:00:43 +00:00
Dylan Baker
52cf2d05a7 meson: don't generate file into subdirs
This is unsupported by meson and may become a hard error in the future.

Fixes: 5adfc8602c
       ("lima/ppir: move sin/cos input scaling into NIR")
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-09-11 08:35:05 -07:00
Kenneth Graunke
73b70b4952 iris: Set bo->reusable = false in iris_bo_make_external_locked
This fixes a missing bo->reusable = false in iris_bo_export_gem_handle.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2019-09-11 08:10:47 -07:00
Kenneth Graunke
06370c3167 iris: Finish initializing the BO before stuffing it in the hash table
Other threads may pick it up once it's in the hash table.  Not known
to fix anything currently.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2019-09-11 08:10:47 -07:00
Marek Olšák
9a59ad87df radeonsi/gfx9: honor user stride for imported buffers
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-11 11:03:31 -04:00
Marek Olšák
b97c5edd7a prog_to_nir, tgsi_to_nir: make sure kill doesn't discard NaNs
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-09-11 10:59:27 -04:00
Vasily Khoruzhick
32ea4c2c5e lima: set .out_sync field of req in lima_submit_start()
Looks like .out_sync wasn't set in lima_submit_start(), as result
submit completion fence was never signalled.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-09-10 21:49:53 -07:00
Kenneth Graunke
c6d40b5182 gallium: Fix util_format_get_depth_only
This is a pipe format, not a boolean.

Fixes: 5849e0612c ("gallium/auxiliary: Add util_format_get_depth_only() helper.")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-09-10 15:49:29 -07:00
Rob Clark
6c19d37331 freedreno/a6xx: fix 3d tex layout
Fixes dEQP-GLES3.functional.texture.specification.texstorage3d.size.3d_2x2x2_2_levels

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-09-10 22:08:33 +00:00
Rob Clark
85a23a8991 freedreno/a6xx: don't tile things that are too small
If the lowest (largest) mipmap level is too small to tile, then don't
bother pretending.

Note that this requires initializing pipe->screen before
fd_resource_level_linear() is called.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-09-10 22:08:33 +00:00
Caio Marcelo de Oliveira Filho
15e439071d iris: Enable ARB_gl_spirv and ARB_spirv_extensions
This will also "unlock" OpenGL 4.6 for Iris!

v2: Also enable PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [v1]
2019-09-10 14:36:46 -07:00
Caio Marcelo de Oliveira Filho
eca8032f20 gallium: Add ARB_gl_spirv support
The PIPE_CAP_GL_SPIRV capability enables ARB_gl_spirv and
ARB_spirv_extensions, and will make sure the corresponding SPIR-V
capabilities and extensions lists are initialized.

The additional PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS capability enables
the support for Variable Pointers in SPIR-V shaders.  This depends on
the driver and is not mandatory for ARB_gl_spirv support.

v2: Add a PIPE_CAP for Variable Pointers.  (Marek)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [v1]
2019-09-10 14:36:46 -07:00
Kenneth Graunke
077a1952cc iris: Fix constant buffer sizes for non-UBOs
Since the system value refactor, we've accidentally only been setting
cbuf->buffer_size in the UBO case, and not in the uploaded-constants
case.  We use cbuf->buffer_size to fill out the SURFACE_STATE entry,
so it needs to be initialized in both cases.

Fixes: 3b6d787e40 ("iris: move sysvals to their own constant buffer")
2019-09-10 10:53:15 -07:00
Marek Olšák
ef919d8dcb radeonsi: remove redundant si_texture offset and size fields
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
e4c84d8678 radeonsi: move texture storage allocation outside of radeonsi
possible code sharing with radv

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
58ccadfc5c radeonsi: move HTILE allocation outside of radeonsi
ac_surface computes it for amdgpu.
radeon_drm_surface computes it for radeon.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
30a1dd0ee6 radeonsi: handle NO_DCC early
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
7d4a10a29f ac/surface: add RADEON_SURF_NO_FMASK
This controls FMASK and CMASK computation for MSAA.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
6633863150 r300,r600,radeonsi: set winsys_handle::stride,offset in drivers, not winsyses
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
5ac6908263 r300,r600,radeonsi: read winsys_handle::stride,offset in drivers, not winsyses
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
d95afd8b9e radeonsi/gfx10: fix wave occupancy computations
Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
42ea0b7b52 radeonsi: only support at most 1024 threads per block
LLVM 10 won't support 2048.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
c1e08cb6d5 radeonsi: disable DCC when importing a texture from an incompatible driver
and unify the code.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
28adf0d00c radeonsi/gfx10: don't call gfx10_destroy_query with compute-only contexts
This fixes a crash.

Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
2f42d4cacc radeonsi/gfx10: use fma for TGSI_OPCODE_FMA
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Lepton Wu
263136fb5d virgl: Fix pipe_resource leaks under multi-sample.
Fixes: 900a80f9e4 ("virgl: virgl_transfer should own its virgl_resource")

Signed-off-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-09-10 03:42:55 +00:00
Kenneth Graunke
410894c643 iris: Avoid flushing for cache history on transfer range flushes
The VBO module maps a buffer with GL_MAP_FLUSH_EXPLICIT, and keeps
appending data, and calling glFlushMappedBufferRange().  We were
invalidating the VF cache each time it flushed a new range, which
results in a ton of VF flushes.

If the contents of the destination in the target range are undefined
(never even possibly written), this patch makes us assume that it's
likely not in the cache and so cache invalidations are required.  If
the destination range is defined, we continue cache flushing as we may
need to expunge stale data.

This eliminates 88% of the VF cache invalidates on Manhattan 3.0.
Improves performance in Manhattan 3.0 on my Icelake 8x8 with the GPU
frequency locked to 700Mhz by 0.376724% +/- 0.0989183% (n=10).
2019-09-09 15:08:22 -07:00
Kenneth Graunke
7d28e9ddd6 iris: Optimize out redundant sampler state binds
This cuts roughly 85% of the 3DSTATE_SAMPLER_STATE_POINTERS_PS calls in
the J2DBench images test.  For some reason, the state tracker is calling
bind_sampler_state with the same sampler state in a bunch of cases.
2019-09-09 11:55:27 -07:00
Kenneth Graunke
325e25d689 iris: Add support for the always_flush_cache=true debug option.
This can be useful for debugging missing flushes.
2019-09-09 11:55:27 -07:00
Adam Jackson
366b2e5c19 mesa: Eliminate gl_config::rgbMode
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-09-09 14:12:57 -04:00
Adam Jackson
78e0fa6bb2 mesa: Eliminate gl_config::have{Accum,Depth,Stencil}Buffer
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-09-09 14:12:57 -04:00
Adam Jackson
c4990b7b19 mesa: Remove unused gl_config::indexBits
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-09-09 14:12:57 -04:00
Adam Jackson
04bef9a0a6 gallium/xlib: Fix an obvious thinko
x == !GLX_DIRECT_COLOR is a fancy way of writing x == 0, which is
clearly not what was meant.
2019-09-09 14:12:57 -04:00
Kenneth Graunke
9173459b95 iris: Ignore line stipple information if it's disabled
The line stipple pattern and factor only matter if line stippling is
actually enabled.  Otherwise, we can safely ignore it.

PBO upload may give us zero for line stipple information, while normal
drawing tends to give us an actual stipple pattern such as 0xffff.  This
was causing us to flag IRIS_DIRTY_LINE_STIPPLE way too often, leading to
useless 3DSTATE_LINE_STIPPLE commands, which are non-pipelined and thus
very expensive.

Improves performance in Manhattan 3.0 on Skylake GT4e by
0.149261% +/- 0.0380796% (n=210).  On an Icelake 8x8 with the GPU
frequency locked at 700Mhz, improves by 0.423756% +/- 0.222843% (n=3).
2019-09-09 10:55:20 -07:00
Vasily Khoruzhick
fbd5d9ebb5 lima/ppir: drop fge/flt/feq/fne options
These are supposed to be lowered into sge/slt/seq/sne equivalents.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-09-09 10:25:30 -07:00
Vasily Khoruzhick
576341324d lima: run opt_algebraic between int_to_float and boot_to_float for vs
int_to_float emits ftrunc and ftrunc lowering generates bool ops.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-09-09 10:25:30 -07:00
Vasily Khoruzhick
996f1b6174 lima/gpir: fix warning in gpir disassembler
Fixes following warning:

../src/gallium/drivers/lima/ir/gp/disasm.c: In function ‘print_src’:
../src/gallium/drivers/lima/ir/gp/disasm.c:241:20: warning: array subscript 28 is above array bounds of ‘char[5]’ [-Warray-bounds]
  241 |              "xyzw"[src - gpir_codegen_src_attrib_x]);

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-09-09 10:25:30 -07:00
Vasily Khoruzhick
e6dbf6d948 lima/gpir: lower fceil
GP doesn't support fceil so we need to lower it.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-09-09 10:25:30 -07:00
Connor Abbott
c64f30546d lima/gpir: Disallow moves for schedule_first nodes
The entire point of schedule_first is that the node has to be scheduled
as soon as possible without any moves because it doesn't produce a
proper floating-point value, or its value changes depending on where you
read it. We were still introducing a move for preexp2 in some cases
though, even if it got scheduled as soon as possible, which broke some
exp() tests. Fix that.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-09-09 17:42:19 +07:00