Commit graph

11026 commits

Author SHA1 Message Date
Francisco Jerez
8bc3821520 intel/fs/xe2+: Disable bank conflict mitigation pass for now.
Reworks:
* Added a TODO comment.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27165>
2024-01-20 19:55:31 +00:00
Francisco Jerez
6efcba9e36 intel/ir/xe2+: Add support for 32 SBID tokens to performance model.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27165>
2024-01-20 19:55:31 +00:00
Caio Oliveira
5552ffd0f3 intel: Use an intel enum for cmat scope
While convenient, it was not necessary to use the mesa_scope in
intel_device_info.

Having a Intel specific enum here will help later the efforts
of serialization of intel_device_info.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27164>
2024-01-19 22:09:25 +00:00
José Roberto de Souza
b571ae6e7a intel: Make memory heaps consistent between KMDs
Xe KMD reports SMEM size as half of RAM while i915 returns the whole
RAM size, so to keep it consistent here adjusting the values
returned by i915 KMD.

The free i915 SMEM also needs to be ajusted but as this is needed by
both KMDs because KMD uAPIs only reports free memory for applications
running elevated privileges, so this was moved to
intel_device_info_ajust_memory() to be shared by both KMD backends.

sram.mappable.size asserts had to be removed from i915 code paths
because of this adjustment.

anv_compute_sys_heap_size() was dropped in ANV and reduce in HASVK
because adjustments are now done in intel/dev level.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26567>
2024-01-19 03:36:07 +00:00
José Roberto de Souza
ca94420d6d intel/dev: Reduce usage of intel_device_info_compute_system_memory()
This function should only be used when i915 versions that don't have
DRM_I915_QUERY_MEMORY_REGIONS.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26567>
2024-01-19 03:36:07 +00:00
Caio Oliveira
4dbf9181cd intel/compiler: Fix rebuilding the CFG in fs_combine_constants
When building the CFG the instructions are taken of the list in
fs_visitor and added to the lists inside each block.  The single
"exec_node" in the instruction is used for those memberships.

In the case the pass rebuilt the CFG, it had no instructions, so
calculate_cfg() had nothing to work with.  For now fix the bug by
pulling all the instructions back to the original list.

We can do better here, but punting until upcoming work on
CFG itself.

Issue found in an unpublished CTS test.  Small reproduction in our
unit tests now enabled.

Fixes: 65237f8bbc ("intel/fs: Don't add MOV instructions to DO blocks in combine constants")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27131>
2024-01-19 01:59:36 +00:00
Caio Oliveira
e9bfdcf576 intel/compiler: Add couple of tests for fs_combine_constants
Add a simple test to kick off the infrastructure.   And also a test
(for now disabled) that fails because the code is returning an
empty shader.  Next patch will fix and enable it.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27131>
2024-01-19 01:59:36 +00:00
Tapani Pälli
02d7f5e4ff anv: expand pre-hiz data cache flush to gfx >= 125
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27132>
2024-01-18 19:45:04 +00:00
Ian Romanick
7481d61a5d intel/compiler: Track mue_compaction and mue_header_packing flags in brw_get_compiler_config_value
v2: Use u_foreach_bit64. Suggested by Lionel.

Fixes: 48885c7fe3 ("intel/compiler: load debug mesh compaction options once")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26993>
2024-01-18 19:20:12 +00:00
Ian Romanick
6f237a23c7 intel/compiler: Track lower_dpas flag in brw_get_compiler_config_value
This user-settable flag affects compiler output, so it should be tracked
in the cache hash.

Fixes: 3756f60558 ("intel/fs: DPAS lowering")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Lionel Landwerlin
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26993>
2024-01-18 19:20:12 +00:00
Ian Romanick
2741c6464c intel/compiler: Use u_foreach_bit64 in brw_get_compiler_config_value
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Lionel Landwerlin
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26993>
2024-01-18 19:20:12 +00:00
Ian Romanick
951e08fc18 intel/compiler: Disable DPAS instructions on MTL
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3756f60558 ("intel/fs: DPAS lowering")
Closes: #10376
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26993>
2024-01-18 19:20:12 +00:00
Hans-Kristian Arntzen
4ab6d7e753 wsi/x11: Add drirc option to ignore SUBOPTIMAL.
Talos Principle and related games on that engine fail to handle
SUBOPTIMAL properly. Adds an option to ignore SUBOPTIMAL and pretend
it's SUCCESS.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27037>
2024-01-18 17:23:32 +00:00
Jordan Justen
05b628b5af intel/dev/common: Add xe2 support to get_l3_list()
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26742>
2024-01-18 14:16:18 +00:00
José Roberto de Souza
df0fe0dfbd intel/genxml/xe2: Remove L3ALLOC
This register don't exist in Xe2 and there is no Bspec page with
another register to be programmed with L3 allocation layout so
intel_get_l3_config() can also always return NULL for Xe2.

Still allowing intel_get_l3_config() to return non-null because
intel_l3_config is used to calculate TBIMR parameters, see
intel_calculate_tile_dimensions().

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26742>
2024-01-18 14:16:17 +00:00
David Heidelberg
4ff77f08e4 ci/deqp: uprev deqp-runner for Linux too to 0.18.0
Previous commit upreved deqp only for the Android

Fixes: 1ff4687e86 ("ci: uprev deqp-runner from 0.16.1 to 0.18.0")

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>

[Eric]
- rename the deqp-runner version to DEQP_RUNNER_VERSION instead of DEQP_VERSION
- update image tags
- fix expectations lists

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27062>
2024-01-16 15:14:20 +00:00
Lionel Landwerlin
56eb09480b anv: rename video command file
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26989>
2024-01-15 12:28:50 +00:00
Lionel Landwerlin
51d63f2236 anv: move compute/ray-tracing commands to their own file
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26989>
2024-01-15 12:28:50 +00:00
Lionel Landwerlin
cfe894e1e9 anv: move draw commands to their own file
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26989>
2024-01-15 12:28:50 +00:00
Lionel Landwerlin
ddc18b4e78 anv: move generated draw flush helper to its own file
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26989>
2024-01-15 12:28:49 +00:00
Lionel Landwerlin
df1dc882cb anv: fix missing header
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26989>
2024-01-15 12:28:49 +00:00
Lionel Landwerlin
74c8edd288 anv: fix include guards
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26989>
2024-01-15 12:28:49 +00:00
Lionel Landwerlin
6bb3ae99c5 anv: export descriptor flushing functions
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26989>
2024-01-15 12:28:49 +00:00
Lionel Landwerlin
7e111268f1 intel/hang_viewer: add aux-tt view
Allows you to visualize the AUX-TT.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27058>
2024-01-15 11:16:40 +00:00
Lionel Landwerlin
78a881af43 intel/genxml: add GAM done register description
Useful if you encounter some kind of pagefault (including with
AUX-TT).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27058>
2024-01-15 11:16:40 +00:00
Lionel Landwerlin
547c2f3d3f intel/genxml: add CCS_INSTDONE register
Gives us the ability to check whether the compute command streamer is
hung.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27058>
2024-01-15 11:16:40 +00:00
Lionel Landwerlin
f78fac623a intel/decoder: don't ignore BT entries at offset 0
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27058>
2024-01-15 11:16:40 +00:00
Lionel Landwerlin
7107ed55c0 intel/decoder: make vertex data decoding optional
When capturing INTEL_DEBUG=capture-all and the application has like
1Gb of vertex data, you might not want to actually decode it when
looking at the error state.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27058>
2024-01-15 11:16:40 +00:00
Tapani Pälli
36f428f1de anv: check for wa 16013994831 in emit_so_memcpy_end
We are toggling preemption on/off during streamout, this is also
happening on gfx12 platforms, not just dg2.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27002>
2024-01-15 08:36:29 +00:00
Vinson Lee
73835874a8 intel/disasm: Remove duplicate variable reg_file
Fix defects reported by Coverity Scan.

Evaluation order violation (EVALUATION_ORDER)
write_write_typo: In reg_file = reg_file = brw_inst_dpas_3src_dst_reg_file(devinfo, inst),
reg_file is written twice with the same value.

Fixes: 1c92dad5cb ("intel/disasm: Disassembly support for DPAS")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27056>
2024-01-15 07:46:12 +00:00
Lionel Landwerlin
ff6041afdf intel/aux_map: fix fallback unmapping range on failure
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7c6faa1efe ("intel/aux_map: introduce ref count of L1 entries")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27057>
2024-01-15 08:08:21 +02:00
José Roberto de Souza
49fe060b5f anv: Fix PAT entry for userptr in integrated GPUs
Fixes: 060439bdf0 ("anv: Add ANV_BO_ALLOC_IMPORTED")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27040>
2024-01-12 21:32:49 +00:00
Caio Oliveira
1a31970946 intel/compiler/xe2: Implement instruction compaction for DPAS.
These use different tables but map to the same bits, so it is just
a matter of picking the right tables for the instruction.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
6e56a4b474 intel/compiler/xe2: Fix for the removal of AccWrCtrl.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
7f39e51dd5 intel/compiler/xe2: Add extra flag registers.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
f974eacab3 intel/compiler/xe2: Fix for the removal of most predication modes.
Reworks:
* Remove changes to fixup_nomask workaround since it applies only for
  Gfx12 family.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
f79123e1d9 intel/compiler/xe2: Fix for NibCtrl field removal.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
7db3f0b1c1 intel/compiler/xe2: Implement instruction compaction.
Reworks:
* Handle DPAS in has_3src_unmapped_bits.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
57ba9c176c intel/compiler/xe2: Implement codegen of compact instructions.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
d8ba1d63bc intel/compiler: Add assume() checks to brw_compact_inst_(set_)bits().
Similar to the preconditions of brw_inst_(set_)bits().

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
4a24f49b57 intel/compiler/xe2: Implement codegen of three-source instructions.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
e10e7d5aa3 intel/compiler/xe2: Implement codegen of indirect immediates.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
294bdbb253 intel/compiler/xe2: Implement codegen of 2-source instruction operands.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
72bbfa8e8d intel/compiler/xe2: Implement codegen of general instruction controls.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
066e6c6234 intel/compiler/xe2: Add Xe2 bounds to FF() macro.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Tapani Pälli
810c1f7747 hasvk: remove gfx9 specific cs stall from emit_ps_depth_count
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26997>
2024-01-12 14:01:08 +00:00
Tapani Pälli
30c148fd16 hasvk: remove softpin (GFX_VERx10 >= 90) related code
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26997>
2024-01-12 14:01:08 +00:00
Tapani Pälli
ed2743258a hasvk: remove gfx9 specific code from emit_sample_pattern
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26997>
2024-01-12 14:01:08 +00:00
Tapani Pälli
4d3d3a495f hasvk: remove cmd_buffer_ray_query_globals function decl
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26997>
2024-01-12 14:01:08 +00:00
Rohan Garg
91798bab2d anv: refactor emit_dynamic_buffer_binding_table_entry
Refactor emit_dynamic_buffer_binding_table_entry to emit a null surface
state when the descriptor has no assocaited buffers allowing us to drop
the same check elsewhere.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27005>
2024-01-12 11:55:41 +00:00