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Author SHA1 Message Date
Alyssa Rosenzweig
6b551d9f36 pan/bi: Add initial fcmp test 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
778e27b5ac pan/bit: Interpret CMP 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
71501972e9 pan/bit: Prepare condition evaluation for vectors 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
0b8724c340 pan/bi: Relax double-abs condition 
Only if both ports (<==> registers) same.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
81156ad55a pan/bi: Pack fma.fcmp16 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
7a689470d0 pan/bi: Factor out fp16 abs logic 
Also used for fcmp16

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
c94d41ad7c pan/bi: Pack FMA 32 FCMP 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
1520131d82 pan/bi: Fix source mod testing for CMP 
Outputs u32.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
12ca99f2c1 pan/bi: Structify ADD ICMP 32 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
ddcefefa7d pan/bi: Structify FMA ICMP 16 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
3d41468e7d pan/bi: Structify FMA ICMP 32 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
527d7303ca pan/bi: Structify ADD FCMP16 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
74795dd328 pan/bi: Structify FMA FCMP16 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
28afe3037a pan/bi Strucitfy ADD FCMP 32 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
c861292ce2 pan/bi: Structify FMA FCMP 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
7fe3c145d9 pan/bi: Remove bi_round_op 
No purpose.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
95fc71ece2 pan/bi: Deduplicate csel/cmp cond 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
df486689c0 pan/bi(t): Fix SELECT tests 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
814f2f1d33 pan/bi: Add CSEL.8 opcode 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
e23d191245 pan/bi: Add FCMP.GL.v2f16 on ADD opcode 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
b4f2d3a51c pan/bi: Add 64-bit int compares 
Likewise.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
52cc7165c6 pan/bi: Add some 8-bit compares 
Not all but enough to see the pattern.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
2f286eed2a pan/bi: Add CSEL.64 opcode 
Chain twice for full 64-bit CSEL.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
100edfe26d pan/bi: Add bool->float opcodes 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
 2020-04-28 17:17:48 +00:00
Samuel Pitoiset
523e9603d3 radv: enable FMASK for color attachments only 
The reason behind this is that FMASK requires CMASK and also that
FMASK for non color attachments looks unnecessary. It's currently
much easier to add this simple check because the driver tries to
always enable DCC first and if we enable FMASK only if CMASK, we
might loose some FMASK compressions.

This helps fixing some new robustness2 tests which fails because
only FMASK is enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4783>
 2020-04-28 17:23:05 +02:00
Jason Ekstrand
81ac741f89 anv: Expose CS workgroup sizes based on a maximum of 64 threads 
Otherwise, we'll hit asserts in brw_compile_cs.

Fixes: cf12faef61 "intel/compiler: Restrict cs_threads to 64"
Closes: #2835
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4746>
 2020-04-28 14:51:08 +00:00
Jason Ekstrand
86f67952d3 intel/devinfo: Compute the correct L3$ size for Gen12 
Fixes: 8125d7960b "intel/dev: Add preliminary device info for Tigerlake"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Clayton Craft <clayton.a.craft@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4782>
 2020-04-28 14:34:17 +00:00
Bas Nieuwenhuizen
7262c743dc radv: Determine memory type for import based on fd. 
This would be necessary for an application to figure out if the
memory was allocated using a memory type with VK_MEMORY_PROPERTY_PROTECTED_BIT.

It also allows one to determine VRAM vs. GTT etc.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
 2020-04-28 15:45:03 +02:00
Bas Nieuwenhuizen
f30983be3a radv/winsys: Add function to get domains/flags from fd. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
 2020-04-28 15:45:00 +02:00
Bas Nieuwenhuizen
bec9285027 radv: Stop using memory type indices. 
Lots of extra coding was involved in managing them.

And for protected memory I was thinking of making a function that
goes from domain+flags to memory types, which can reuse this array.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
 2020-04-28 15:44:56 +02:00
Bas Nieuwenhuizen
4a8d172d3f radv: Use actual memory type count for setting app-visible bitset. 
Otherwise we might make a bitset that is too large.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
 2020-04-28 15:44:27 +02:00
Bas Nieuwenhuizen
8e03cf15f9 radeonsi: Count planes for imported textures. 
For the DRI2 lowered YUV import separate pipe_resources get created
but in the end the first resource just gets asked for NPLANES.

Since

1) (Almost) everything uses the first resource + a plane index in the
  Gallium interface.
2) This mirrors non-imported textures.

lets fix this in the driver.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4779>
 2020-04-28 11:16:03 +00:00
Gert Wollny
6747a984f5 r600: Enable tesselation for NIR 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
b6d4452661 r600/sfn: Add tesselation shaders 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
d77b81ce50 r600/sfn: Add lowering passes for Tesselation IO 
Lower the input and output intrinsics to r600 specific LDS intrinsics

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
1b3e103d0b r600/sfn: Move removing of unused variables 
It doesn't make sense to do this in the optimization loop

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
74e0a0a723 r600/sfn: Handle LDS output in VS 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
f102301cc4 r600/sfn: derive the GS from the vertex stage for a common interface 
The GS can also provide the primid

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
f7df2c57a2 r600/sfn: extract class to handle the VS export to different stages 
This code can be shared with the TESS_EVAL shader

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
38038b369f r600/sfn: Move some shader base methods to the public interface 
This will be needed for handling the VS stage export better.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
93f5f9e584 r600/sfn: Add methods to valuepool to get a vector of values 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
7cbca9cf64 r600/sfn: Move emission of barrier from compute shader to shader base 
Tess shaders also use these barriers.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
46a3033b43 r600/sfn: Emit some LDS instructions 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
a122303711 r600/sfn: Handle umul24 and umad24 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
7e064659cb r600/sfn: Add IR instruction to fetch the TESS parameters 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
075ea32e48 r600/sfn: Add TF write instruction 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
230beac5f8 r600/sfn: Add LDS instruction to assembly conversion 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
b9d175bed2 r600/sfn: Add LDS IO instructions to r600 IR 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
172868167e r600/sfn: Don't emit inline constants in the r600 IR 
This can be handled when lowering to assembly, and it makes testing
for indirect buffer and sampler access easier.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00
Gert Wollny
9bc6c135ac r600/sfn: simplify UBO lowering pass 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
 2020-04-28 08:06:33 +00:00