Commit graph

1373 commits

Author SHA1 Message Date
Eric Engestrom
320018be77 meson: s/radv_extensions/radv_extensions_c/ to respect var convention
Suggested-by: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-10-17 19:07:09 +01:00
Eric Engestrom
1f0e80f897 meson: track python script dependency
Suggested-by: Andres Gomez <agomez@igalia.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2017-10-17 19:07:03 +01:00
Eric Engestrom
cde7859273 meson: add missing radv_extensions.c generation for libvulkan_radeon
Fixes: 17201a2eb0 "radv: port to using updated anv entrypoint/extension generator."
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
2017-10-17 16:19:21 +01:00
Dave Airlie
35c66f3e40 radv/image: bump all the offset to uint64_t.
So one of the CTS tests tries to allocate a 16384x1 2048 array
texture. This overflows a bunch of calculations when we want it
tiled as the heights goes to 128.

addrlib returns us the correct size (16GB or so), but we mangle
it in the htile calcs due to the 32-bit offset fields, then
userspace gives us the reduced number and we try to allocate
it on a heap and things blow up.

We really need to give the app back the correct size for the
image so we can blow up properly in memory allocation later.

This should fix hangs in
dEQP-VK.pipeline.render_to_image.core.1d_array.huge.width_layers.r8g8b8a8_unorm_d32_sfloat_s8_uint
since
Fixes: ad3d98da9f (radv: enable tc compatible htile for d32s8 also.)

Now there's an open question if we should be enabling tc-compat
htile at all for shallow textures like the above.

This might cause some other wierd side effects in CTS even
without the tc compat so:
Cc: "17.2" <mesa-stable@lists.freedesktop.org>

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-17 08:28:48 +01:00
Dave Airlie
17201a2eb0 radv: port to using updated anv entrypoint/extension generator.
This ports radv to using the anv entrypoint/extension generator
code.

No differences on enabled extensions list in vulkaninfo.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-17 16:50:32 +10:00
Dave Airlie
c00256a12c radv: enable VK_KHX_multiview always.
This was in the wrong place.

Fixes: ba51ad2f2 (radv: Expose VK_KHX_multiview.)
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-17 16:48:14 +10:00
Samuel Pitoiset
f16382d35b radv: update ia_multi_vgt when executing secondary buffers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-16 14:50:30 +02:00
Samuel Pitoiset
47d7d18613 radv: be smarter with the draw packets when executing secondary buffers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-16 14:50:27 +02:00
Samuel Pitoiset
b253f3189a radv: always dirty some states after executing secondary buffers
The spec requires the number of buffer to be greater than 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-16 14:09:51 +02:00
Samuel Pitoiset
4e65b4ea4b radv: be smarter with pipelines when emitting secondary buffers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-16 14:09:51 +02:00
Samuel Pitoiset
0c1aecf177 radv: do not allocate CMASK for non-MSSA images with 128 bit formats
This saves some useless CMASK initializations/eliminations in
the Vulkan SSAO demo.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-14 12:25:48 +02:00
Samuel Pitoiset
a4c08c8cd5 radv: set correct INDEX_TYPE for indexed indirect draws on GFX9
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-14 12:05:19 +02:00
Samuel Pitoiset
3e5f27faf3 radv: add the draw count buffer to the list of buffers
My guess is that the GPU is going to report VM faults if
vkCmdDrawIndirectCountAMD() (and friends) are used.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-14 12:05:19 +02:00
Dave Airlie
fb972ed4e5 radv: take unsafe_math and sisched into account when hashing shaders.
We want to generate different variants for sisched and unsafe_math
shader variants, so add them to the hash key.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-12 23:46:55 +01:00
Marek Olšák
11adea4b24 ac: add radeon_info::has_sync_file
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 21:04:56 +02:00
Marek Olšák
5f2073be32 ac/surface: add ac_surface::is_displayable
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 19:03:33 +02:00
Marek Olšák
c3f3685fd6 amd/addrlib: add Addr2IsValidDisplaySwizzleMode
Some "standard" (_S) swizzle modes are displayable on Raven,
even though the micro tile mode says it's not displayable.
Expose the addrlib function to the driver.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 19:03:33 +02:00
Dave Airlie
6049fa454e radv: don't crash if cache is disabled.
If you set MESA_GLSL_CACHE_DISABLE, radv crashed.

Fixes: fd24be134f (radv: make use of on-disk cache)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-10-12 14:14:43 +02:00
Samuel Pitoiset
4f42ea4dcf radv: use CLEAR_STATE for initializing some registers
Based on RadeonSI.

This improves some Vulkan demos by +1% to +3%.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-12 09:17:43 +02:00
Samuel Pitoiset
65dcff7a26 radv: add has_clear_state and enable it on CIK+ only
This will allow us to emit the CLEAR_STATE packet instead
of a bunch of useless packets when doing CS initialization.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-12 09:17:40 +02:00
Samuel Pitoiset
c74ed3966e radv: do not set registers for merged ES-GS on GFX9
Based on RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-12 09:17:38 +02:00
Samuel Pitoiset
1789cac6dd radv: move the raster config emission in si_set_raster_config()
Similar to RadeonSI, also only call this function for <= VI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-12 09:17:35 +02:00
Timothy Arceri
0061a90550 radv: remove duplicate line of code
The same line of code is a few lines above.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-10-12 08:52:39 +11:00
Timothy Arceri
fd24be134f radv: make use of on-disk cache
If the app provided in-memory pipeline cache doesn't yet contain
what we are looking for, or it doesn't provide one at all then we
fallback to the on-disk cache.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-12 08:52:38 +11:00
Timothy Arceri
1421625292 radv: create on-disk shader cache
This is the drivers on-disk cache intended to be used as a
fallback as opposed to the pipeline cache provided by apps.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-12 08:52:38 +11:00
Timothy Arceri
7664aaf331 radv: remove duplicate debug_flags field
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-12 08:52:38 +11:00
Bas Nieuwenhuizen
96f80c8d4d radv: Only set the MTYPE flags on GFX9+.
Older kernels fail the va_op with this flag set. If the kernel
supports GFX9 usefully, it will also support this flag.

Fixes: e8d57802fe "radv/gfx9: allocate events from uncached VA space"
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-11 07:57:33 +10:00
Dave Airlie
2c61594d84 radv: lower ffma in nir.
So it appears the Vulkan SPIR-V fma opcode can be equivalent to a
mad operation, and the fma hw opcode on AMD hw is issued like a double
opcode so is slower. Also the radeonsi stack does this.

This appears to improve performance on a number of games from Feral,
and thanks to Feral for noticing the problem.

I'm reposting this one as Marek indicated he thinks this is what
we should be doing on AMD hw.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-11 07:31:27 +10:00
Alex Smith
25d76fd658 radv: Add R16G16B16A16_SNORM fast clear support
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-11 07:29:43 +10:00
Dave Airlie
4adc456580 radv: export KHR_relaxed_block_layout
This seems to pass all the cts tests it enables.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-10 13:22:44 +10:00
Marek Olšák
7b697c8b78 amd: move r600d_common.h into r600g
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:27:06 +02:00
Marek Olšák
76997e9133 radeonsi: shrink r600d_common.h and stop using it
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:27:05 +02:00
Samuel Pitoiset
7824cb4b03 radv: configure VGT_VERTEX_REUSE at pipeline creation
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-09 10:06:19 +02:00
Samuel Pitoiset
b09b43b166 radv: do not need to zero-init ds/raster states
Already done when creating the pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-09 10:06:17 +02:00
Samuel Pitoiset
d4652e7c86 radv: remove unused fields in radv_raster_state
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-09 10:06:15 +02:00
Samuel Pitoiset
6732a8369a radv: set ALPHA_TO_MASK_ENABLE at blend state init
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-09 10:05:06 +02:00
Samuel Pitoiset
5848565ee3 radv: emit PA_SU_POINT_{SIZE,MINMAX} in si_emit_config()
These registers don't change during the lifetime of the
command buffer, there is no need to re-emit them when
binding a new pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-09 10:05:04 +02:00
Samuel Pitoiset
aab1537568 radv: allow launching waves out-of-order for compute
Ported from RadeonSI, and -pro seems to enable it as well.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-09 10:04:17 +02:00
Samuel Pitoiset
c8ea55ddda radv: convert all COMPUTE operations to the RADV_META_SAVE_XXX flags
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:06 +02:00
Samuel Pitoiset
213f86e514 radv: add RADV_META_SAVE_COMPUTE_PIPELINE flag
This will allow use to merge the compute save/restore helpers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:06 +02:00
Samuel Pitoiset
ba3dc3519d radv: add radv_meta_save() helper
And merge radv_meta_save_novertex() with
radv_meta_save_graphics_reset_vport_scissor_novertex().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:06 +02:00
Samuel Pitoiset
8d91f4e45f radv: merge radv_meta_{save,restore}_pass() with RADV_META_SAVE_PASS
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:06 +02:00
Samuel Pitoiset
55ee532932 radv: convert all GFX operations to the RADV_META_SAVE_XXX flags
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:05 +02:00
Samuel Pitoiset
807f2d4f33 radv: introduce the concept of meta save flags
This will allow us to save/restore the different states on-demand
based on the meta operation. For now, this saves/restores all
states. Compute will follow once the graphics part is done.

The main idea is to merge all save/restore helpers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:05 +02:00
Samuel Pitoiset
a3a497c921 radv: remove unused RADV_META_VERTEX_BINDING_COUNT
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:05 +02:00
Samuel Pitoiset
b269ed3d94 radv: select the pipeline outside of the loop when decompressing htile
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:05 +02:00
Samuel Pitoiset
507df35939 radv: add radv_htile_enabled() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:05 +02:00
Marek Olšák
bcd3e761a3 ac: properly document a buffer.store LLVM workaround
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Bas Nieuwenhuizen
4ffb9890ef radv: Enable VK_KHR_maintenance2 extension.
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-06 01:41:29 +02:00
Bas Nieuwenhuizen
0c90ca7d37 radv: Make tess winding order a bit more intuitive.
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-06 01:41:29 +02:00