Commit graph

15814 commits

Author SHA1 Message Date
Marek Olšák
0d8fe2d03b ac/nir/meta: tune clear/copy_buffer performance for gfx6-10.3
Finally, old GPUs have optimal clear/copy_buffer performance, but only
the top dGPU of each generation gets the best behavior.

Other dGPUs might need slightly different conditions.
APUs likely need very different conditions.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31082>
2024-09-17 15:19:32 -04:00
Samuel Pitoiset
656d7e887a radv: fix lowering the view index to an input varying for FS
When multiview is used and the FS is compiled separately with GPL, the
view index still needs to be lowered, otherwise it's crashing later.

The lowering doesn't need to know the previous stage because ViewIndex
is a global thing (ie. it's neither a per-vertex or a per-primitive
varying).

This fixes recent
dEQP-VK.pipeline.pipeline_library.graphics_library.misc.other.view_index_from_device_index_*_pre_rasterization

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31192>
2024-09-17 06:36:08 +00:00
Samuel Pitoiset
fb3b563d1f radv: enable more properties with VK_KHR_maintenance5
They are all supported by the hw and this matches AMD drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31129>
2024-09-17 06:10:54 +00:00
Rohan Garg
85b8579bf6 radv: enable VK_KHR_shader_relaxed_extended_instruction
The extension only affects non semantic instructions that need no
handling in the backend compiler.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30791>
2024-09-16 15:58:35 +00:00
Samuel Pitoiset
32567f6a2a radv: compute shader hash for shaders created without internal cache
VK_KHR_pipeline_binary allows the application to take full control on
the cache and internal caches (disk or in-memory) can be disabled.

Though the shader hash should still be computed, otherwise all pipeline
binaries have a key with all zeroes.

Fixes: 8802612458 ("radv: advertise VK_KHR_pipeline_binary"
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31163>
2024-09-16 13:53:36 +00:00
Samuel Pitoiset
ad68c83f92 radv: fix copying the pipeline binary key
Only the first byte was copied.

Fixes: be06bfcbed ("radv: add initial support for pipeline binaries")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31163>
2024-09-16 13:53:36 +00:00
Samuel Pitoiset
f88cf56087 radv/rt: skip shaders cache for pipelines created with the capture/replay flag
Otherwise, if a pipeline is found in cache it will use a different
shader arena for allocation and the capture replay shader group handles
won't match.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31188>
2024-09-16 12:29:49 +00:00
Hans-Kristian Arntzen
f3c6bbdd8d radv: Always make sure to write the pipeline binary key.
There's nothing in spec that says that key is only written
if data is also written.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Fixes: be06bfcbed ("radv: add initial support for pipeline binaries")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31162>
2024-09-16 11:38:07 +00:00
Ganesh Belgur Ramachandra
62592674e0 amd: fix incorrect PIPE_INTERLEAVE_BYTES size for CDNA chips
The expected PIPE_INTERLEAVE_BYTES size is ADDR_PIPEINTERLEAVE_256B on
gfx940 (or other CDNA based chips). Since CDNA based chips like gfx940
doesn't support image opcodes, it gets gibberish value from the kernel.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30891>
2024-09-16 09:31:49 +00:00
Samuel Pitoiset
ba7e3be425 radv: merge radv_emit_epilog() with radv_emit_ps_epilog_state()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31150>
2024-09-16 07:53:00 +00:00
Samuel Pitoiset
26d8f1a306 aco,radv,radeonsi: move has_epilog to the fragment shader info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31150>
2024-09-16 07:53:00 +00:00
Samuel Pitoiset
b377ddfd04 radv,radeonsi: remove remaining occurrences of TCS epilog
TCS epilog has been removed few months ago.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31150>
2024-09-16 07:53:00 +00:00
Konstantin Seurer
bacf9752f4 radv: Work around broken terrain in Warhammer III
Hiding storage support for depth formats forces the game to take a
different, working path for terrain height map initialization.

cc: mesa-stable

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31152>
2024-09-13 07:48:02 +00:00
Ian Romanick
3b13a0018f radv: Use nir_opt_generate_bfi to generate bitfield_select
v2: Move to radv_optimize_nir_algebraic. Suggested by Georg.

Tested-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31006>
2024-09-13 00:21:00 +00:00
Samuel Pitoiset
e1df6cf499 radv: use radv_get_user_sgpr_loc() more
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31115>
2024-09-12 07:01:36 +00:00
Samuel Pitoiset
190d46b65d radv: precompute more PGM registers for all stages
Less error prone and easier to update for new hardware.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31115>
2024-09-12 07:01:36 +00:00
Samuel Pitoiset
c7a509f55c radv: update PGM register for TES+GS compiled separately with ESO
Not sure why 0xB210 works on GFX10+ because it's supposed to be
0xB320 with/without NGG...

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31115>
2024-09-12 07:01:36 +00:00
Martin Roukala (né Peres)
97624f99a1 radv/ci: run vkcts-navi31-valve pre-merge
We currently have 3 runners with 7950X3D CPUs and 7900XT GPUs which
can rip through VKCTS in ~16 minutes.

Since this is over the 15 minutes threshold, we parallelize the job to
get under 15 minutes, which nets up ~10 minutes total runtime.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31085>
2024-09-12 03:37:18 +00:00
Martin Roukala (né Peres)
7bb80e184c radv/ci: document more vkcts flakes
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31085>
2024-09-12 03:37:18 +00:00
Dave Airlie
7c6e3c70b6 radv/video/enc: report pps overrides in feedback for h265
radv does change h265 usually so report in feedback info.

Fixes: 967e4e09de ("radv/video: add h265 encode support")
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31135>
2024-09-12 10:58:02 +10:00
Dave Airlie
8d08e92199 radv/video: fix encode reference slot counting
This needs the max of slot indices.

Fixes: 54d499818c ("radv/video: add initial support for encoding with h264.")
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31135>
2024-09-12 10:57:58 +10:00
Dave Airlie
e89f4a48fd radv: Fix radeon_enc_code_ue with values over 2^16
This ports this fixes from radeonsi:

138ba42a87 ("radeonsi/vcn: Fix radeon_enc_code_ue with values over 2^16")

Cc: mesa-stable
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31135>
2024-09-12 10:57:18 +10:00
Daniel Schürmann
07b1fd64b7 aco/live_var_analysis: don't set lateKill for p_interp_gfx11 m0 operand
There is no danger of overwriting m0 anymore.

Fixes: dfc13fcf9f ('aco: introduce Operand flag 'CopyKill'')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31127>
2024-09-11 10:36:34 +00:00
Daniel Schürmann
a9d64fa1bd radv: promote VK_NV_compute_shader_derivatives -> VK_KHR_compute_shader_derivatives
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30972>
2024-09-11 08:37:46 +00:00
Samuel Pitoiset
b4ae6eb5fc radv: use radv_upload_indirect_descriptor_sets() in DGC
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31096>
2024-09-10 15:07:04 +00:00
Samuel Pitoiset
7be965bf17 radv: stop allocating upload space for indirect descriptors with DGC
The indirect descriptors are uploaded from the CPU and nothing needs
to be allocated in the DGC buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31096>
2024-09-10 15:07:04 +00:00
Samuel Pitoiset
31875e92aa radv: make the helper that uploads indirect descriptors non-static
It will be used by DGC.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31096>
2024-09-10 15:07:04 +00:00
Samuel Pitoiset
3deebeb20a radv: unify emitting non-indirect/indirect descriptor sets
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31096>
2024-09-10 15:07:04 +00:00
Samuel Pitoiset
bac5ad9f8d radv: rename radv_emit_descriptor_pointers() to radv_emit_descriptors_per_stage()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31096>
2024-09-10 15:07:04 +00:00
Samuel Pitoiset
2c2735083b radv: store the indirect descriptor sets VA to the descriptor state
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31096>
2024-09-10 15:07:04 +00:00
Samuel Pitoiset
529d7ebdcc radv: cleanup some functions that emit shader user SGPRs
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31096>
2024-09-10 15:07:04 +00:00
Daniel Schürmann
dfc13fcf9f aco: introduce Operand flag 'CopyKill'
This flag indicates that the Operand must be copied in order to satisfy register
constraints. The copy is immediately killed by the instruction.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30299>
2024-09-10 09:44:53 +00:00
Daniel Schürmann
91f65d5935 aco/live_var_analysis: use Clobbered flag to calculate additional operand demand
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30299>
2024-09-10 09:44:53 +00:00
Daniel Schürmann
5a6fa8a8eb aco: introduce new Operand flag 'Clobbered'
This flag indicates that the Operand's register gets clobbered by the instruction.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30299>
2024-09-10 09:44:53 +00:00
Daniel Schürmann
1c14013b9e aco/live_var_analysis: Don't attempt to re-insert the same temporary twice into live set
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30299>
2024-09-10 09:44:53 +00:00
Samuel Pitoiset
e621f0c173 radv: rework emitting indirect compute pipelines with DGC
Instead of recreating the packets in the DGC prepare shader, the best
solution is to emit them to a temporary CS object at pipeline creation
time. Then in the DGC prepare shader, the driver just needs to copy
the packets.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31101>
2024-09-10 09:13:44 +00:00
Samuel Pitoiset
8802612458 radv: advertise VK_KHR_pipeline_binary
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
2024-09-10 08:19:52 +00:00
Samuel Pitoiset
b4d6d88c6b radv: add support for importing pipeline binaries
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
2024-09-10 08:19:52 +00:00
Samuel Pitoiset
96a300a3f0 radv: add support for capturing pipeline binaries
When VK_PIPELINE_CREATE_2_CAPTURE_DATA_BIT_KHR is set, implementations
shouldn't store pipeline data to an internal cache.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
2024-09-10 08:19:52 +00:00
Samuel Pitoiset
be06bfcbed radv: add initial support for pipeline binaries
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
2024-09-10 08:19:52 +00:00
Samuel Pitoiset
32a4c9e117 radv: disable the in-memory cache when disableInternalCache is true
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
2024-09-10 08:19:52 +00:00
Samuel Pitoiset
af76f48fc2 radv: make pipeline hashing functions non-static
They will be used to generate pipeline hashes from pCreateInfo.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
2024-09-10 08:19:52 +00:00
Samuel Pitoiset
3423facbd1 radv: store whether a RT pipeline is a library to the shaders cache
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
2024-09-10 08:19:52 +00:00
Samuel Pitoiset
0a15dcf95c radv: store the number of RT stages per pipeline to the shaders cache
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
2024-09-10 08:19:52 +00:00
Samuel Pitoiset
42b1c728b2 radv: store the SHA1 RT stage to the shaders cache
When pipeline binaries are imported, that SHA1 would also need to be
imported in order to deduplicate shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
2024-09-10 08:19:52 +00:00
Samuel Pitoiset
3d2cd4687c radv: rework helpers for serialize/deserialize shaders
They will be used to serialize/deserialize shaders for pipeline
binaries.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30812>
2024-09-10 08:19:52 +00:00
Samuel Pitoiset
0c7896deef Revert "radv: specialize push constant stages with DGC"
This change was wrong but there is nothing testing this. For example,
if we have a pipeline with VS+GS+FS and DGC only updates push constants
for VS. On GFX9+, VS is merged to GS, so the VS push constants info
would be zero and nothing would be emitted.

This reverts commit 45319cb253.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31099>
2024-09-10 07:39:54 +00:00
Dave Airlie
7531f6fd9c radv/anv/video: handling encoding both sps and pps in same buffer
This API should allow encoding these back to back into the same
buffer, so handle it properly.

Cc: mesa-stable
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31086>
2024-09-10 06:03:15 +00:00
Georg Lehmann
8a43b1e7da aco/ra: do not reuse killed vcc
VCC should only be used if nessecary, to keep it free for instructions
that need/prefer it.

Foz-DB Navi31:
Totals from 132 (0.17% of 79395) affected shaders:
Instrs: 832538 -> 832608 (+0.01%); split: -0.03%, +0.04%
CodeSize: 4310888 -> 4301792 (-0.21%); split: -0.22%, +0.01%
Latency: 6238465 -> 6239198 (+0.01%); split: -0.04%, +0.05%
InvThroughput: 5332353 -> 5336363 (+0.08%); split: -0.03%, +0.10%
Copies: 59420 -> 59392 (-0.05%); split: -0.11%, +0.06%
VALU: 459318 -> 459187 (-0.03%); split: -0.03%, +0.00%
SALU: 109208 -> 109081 (-0.12%); split: -0.14%, +0.03%
VOPD: 6426 -> 6557 (+2.04%); split: +2.10%, -0.06%

Foz-DB Navi21:
Totals from 386 (0.49% of 79395) affected shaders:
Instrs: 3254046 -> 3252423 (-0.05%); split: -0.05%, +0.00%
CodeSize: 17839104 -> 17680580 (-0.89%); split: -0.89%, +0.00%
Latency: 24424322 -> 24426242 (+0.01%); split: -0.01%, +0.01%
InvThroughput: 10140681 -> 10143882 (+0.03%); split: -0.01%, +0.04%
SClause: 80731 -> 80738 (+0.01%); split: -0.01%, +0.02%
Copies: 293719 -> 293593 (-0.04%); split: -0.27%, +0.23%
Branches: 126625 -> 126626 (+0.00%); split: -0.00%, +0.00%
VALU: 2086026 -> 2086029 (+0.00%)
SALU: 502641 -> 501012 (-0.32%); split: -0.33%, +0.00%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30902>
2024-09-09 19:48:22 +00:00
Daniel Stone
ed4dc4261e ci/vulkan: Backport dEQP commit to make it less OOMy
It looks like the compute reconvergence tests are slamming us into OOM
on stoney at least; backport a commit which makes this less horrible.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30978>
2024-09-09 16:27:07 +00:00