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Author SHA1 Message Date
Rhys Perry
468ee8b80c aco: implement 16-bit fsat on GFX8 
GFX8 doesn't have v_med3_f16.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26445>
 2023-12-05 16:56:58 +00:00
Rhys Perry
de51a21e26 aco: implement 16-bit derivatives 
These are used by radeonsi.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26445>
 2023-12-05 16:56:58 +00:00
Rhys Perry
997a0884a5 aco: implement 16-bit fsign on GFX8 
GFX8 doesn't have v_med3_i16.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26445>
 2023-12-05 16:56:58 +00:00
Rhys Perry
b7725b072b aco: flush denormals for 16-bit fmin/fmax on GFX8 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26445>
 2023-12-05 16:56:57 +00:00
Samuel Pitoiset
338319741c radv: add DGC support for mesh shader only 
This only implements mesh shaders with DGC because task shaders are
really tricky. I will address them later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
 2023-12-05 14:17:39 +00:00
Samuel Pitoiset
eb3e1bdfe6 radv: only initialize the VTX base SGPR if non-zero with DGC 
Otherwise, its value is incorrect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
 2023-12-05 14:17:39 +00:00
Samuel Pitoiset
1deedc70db radv: only initialize the VBO reg if VBOs are bound with DGC 
With mesh shader there is no VBO at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
 2023-12-05 14:17:39 +00:00
Samuel Pitoiset
400cfa0eba radv: remove never used binds_state for DGC 
This has been removed a while ago.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
 2023-12-05 14:17:39 +00:00
Eric Engestrom
48324e3734 radeonsi/ci: update vangogh piglit expectations 
Looking good there, Vangogh!

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26466>
 2023-12-05 13:34:32 +00:00
Martin Roukala (né Peres)
91076fd390 amd/ci: reduce Renoir's concurrency to 16 
It seems like when we increased the number of tests per shard, we
started overcommitting the Renoir runner, leading to load averages
higher than the 16 CPU threads could handle, while also running at
75-96% memory usage.

By dropping the concurrency to 16, we should be able to reduce this
memory usage while also reducing the execution time.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26501>
 2023-12-05 12:45:44 +00:00
Yonggang Luo
83a5fb9faf util: Fixes note: the alignment of ‘_Atomic long long int’ fields changed in GCC 11. 
This is a improve of https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22121

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23961>
 2023-12-05 09:26:08 +00:00
Eric Engestrom
3115e6e211 amd/ci: reuse .radeonsi-rules in .radeonsi-vaapi-rules 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26480>
 2023-12-05 06:55:21 +00:00
Eric Engestrom
ebaede788e amd/ci: limit radv jobs to radv + aco files changes 
Otherwise, any change in src/amd/ would always trigger all the radv
jobs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26460>
 2023-12-04 20:43:53 +00:00
Eric Engestrom
03d8ea9912 amd/ci: split common amd files list from radeonsi files list 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26460>
 2023-12-04 20:43:53 +00:00
Eric Engestrom
98f0800c94 amd/ci: fix yaml indentation 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26460>
 2023-12-04 20:43:53 +00:00
Friedrich Vock
d6d68ceda1 radv: Enable compute dispatch tunneling 
Compute tunneling can considerably lower the latency of high-priority
compute work. Enabling it is beneficial in cases where high-priority
work is dispatched while the GPU is already busy with other work (e.g.
rendering on GFX). This is the case in VR compositors that dispatch
latency-sensitive compositing work to ACE while GFX is busy rendering
the next frame.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26462>
 2023-12-04 12:32:47 +00:00
Eric Engestrom
778000ec7f radv: update symbols that have become aliases for newer ones 
All of these have been renamed in the spec (usually by being promoted);
renamed them in our code too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26490>
 2023-12-04 10:45:48 +00:00
Felix bridault
059391b631 radv: use 32bit va range for sparse descriptor buffers 
Fixes: 5c5735fd68 ("radv: advertise VK_EXT_descriptor_buffer")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26482>
 2023-12-04 09:59:29 +00:00
Samuel Pitoiset
9027c6d8ca radv: adjust assertions for multi-layer resolves with the HW/FS paths 
Only compute supports layers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
 2023-12-04 08:12:16 +00:00
Samuel Pitoiset
70556739e0 radv: only re-initialize DCC for one level for the HW resolve path 
The source image can only have one level, so only level in the
destination image needs to be re-initialized.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
 2023-12-04 08:12:16 +00:00
Samuel Pitoiset
91aaf0c663 radv: remove unused layers support for the HW/FS resolve paths 
The driver always fallbacks to the compute resolve path when either
the source or destination images have layers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
 2023-12-04 08:12:16 +00:00
Samuel Pitoiset
aae2595390 radv: stop performing redundant resolves with the HW resolve path 
This path was quadratic...
Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
 2023-12-04 08:12:16 +00:00
Samuel Pitoiset
e425f92f3e radv: simplify creating image views for src resolve images 
The Vulkan spec says:

"If samples is not VK_SAMPLE_COUNT_1_BIT, then imageType must be
 VK_IMAGE_TYPE_2D, flags must not contain
 VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT, mipLevels must be equal to 1..."

So, the source image is always 2D with no mipmaps.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
 2023-12-04 08:12:16 +00:00
Eric Engestrom
2cdebf51fd amd/ci: radeonsi is gl, not vk 
Fixes: cf323446e7 ("amd/ci: run gl(es) cts & piglit on radeonsi on vangogh")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26478>
 2023-12-03 13:57:38 +00:00
Eric Engestrom
402210034b radv/ci: add navi21-aco flake 
Failed once in https://gitlab.freedesktop.org/mesa/mesa/-/jobs/52219125
but passed in the automatic retry.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26467>
 2023-12-02 09:33:46 +00:00
Samuel Pitoiset
bd54592487 radv: remove radv_pipeline_key::dynamic_color_write_mask 
When this state is dynamic, the common runtime code sets the write mask
to 0xf which prevents color exports to be removed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26400>
 2023-12-01 15:50:04 +00:00
Martin Roukala (né Peres)
a6f22aa182 radv: disable meshShaderQueries on gfx10.3 
They have been causing hangs intermitently in CI for the past week,
until it finally caught my attention and forced me spend a couple of
hours bisecting the issue.

We'll re-introduce support for it when the issue is fixed.

Fixes: b975d4e800 ("radv: enable meshShaderQueries on GFX10.3")
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26450>
 2023-12-01 15:17:48 +00:00
Samuel Pitoiset
ced313eec8 radv: make sure to prefetch the compute shader for DGC 
It was never prefetched. These two helpers should be refactored with
radv_dispatch() though.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26417>
 2023-12-01 12:25:46 +00:00
Samuel Pitoiset
ab6cf1592f radv: fix bogus interaction between DGC and RT with descriptor bindings 
pipeline_is_dirty was never TRUE because it's emitted in the before
helper. This might fix bad interactions between DGC and RT because
they both use compute shaders and descriptor bindings need to be
re-emitted.

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26417>
 2023-12-01 12:25:46 +00:00
Tatsuyuki Ishi
eb0419a1aa radv: Remove aspect mask "expansion" for copy_image. 
The Vulkan spec says multi-planar images can only be copied on a
per-plane basis. The COLOR_BIT to "all planes" expansion applies to
image memory barriers which is completely unrelated.

Remove the expansion logic to simplify the code. Add assertions to
clearly describe the invariant.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26364>
 2023-12-01 01:52:04 +00:00
Marek Olšák
7ffb65f935 ac: add an IB parser that gathers context rolls 
This is an important performance bottleneck analysis tool.

Try it with radeonsi: AMD_ROLLS=filename app

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
 2023-12-01 01:15:55 +00:00
Marek Olšák
f0cb8852a4 ac: move the IB parsers into ac_parse_ib.c 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
 2023-12-01 01:15:55 +00:00
Marek Olšák
c5fe2780e6 ac: rename ac_parse_ib.c -> ac_ib_parser.c 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
 2023-12-01 01:15:55 +00:00
Peyton Lee
3ec397819e amd: add new hardware ip for vpe 
Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
 2023-12-01 00:23:38 +00:00
Peyton Lee
17c20ceda7 amd,radeonsi: add libvpe 
Signed-off-by: Peyton Lee <peytolee@amd.com>
Signed-off-by: Alan Liu <haoping.liu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
 2023-12-01 00:23:38 +00:00
Lynne
aff59c63eb radv: change queue family order in radv_get_physical_device_queue_family_properties 
Fixes: 748b7f80ef ("radv: Move sparse binding into a dedicated queue.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26428>
 2023-11-30 22:45:49 +00:00
Rhys Perry
5bc27e80c9 ac/nir: fix 32-bit offset global access optimization 
Since 38cff03e58 ("radv: use nir_lower_conv64"), u2u64(a) is replaced
with pack_64_2x32_split(a, 0).

fossil-db (navi31):
Totals from 1203 (1.52% of 79330) affected shaders:
MaxWaves: 33685 -> 33813 (+0.38%)
Instrs: 1407031 -> 1374689 (-2.30%); split: -2.32%, +0.02%
CodeSize: 7088652 -> 6917320 (-2.42%); split: -2.43%, +0.01%
VGPRs: 69276 -> 68988 (-0.42%); split: -0.43%, +0.02%
SpillSGPRs: 982 -> 977 (-0.51%); split: -0.92%, +0.41%
Latency: 12536511 -> 12451605 (-0.68%); split: -0.94%, +0.27%
InvThroughput: 2456803 -> 2431241 (-1.04%); split: -1.09%, +0.05%
VClause: 27624 -> 27832 (+0.75%); split: -1.88%, +2.64%
SClause: 31757 -> 32702 (+2.98%); split: -0.53%, +3.51%
Copies: 90923 -> 91238 (+0.35%); split: -1.47%, +1.81%
Branches: 25127 -> 25128 (+0.00%); split: -0.00%, +0.01%
PreSGPRs: 46025 -> 46068 (+0.09%); split: -0.53%, +0.62%
PreVGPRs: 53944 -> 53488 (-0.85%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26402>
 2023-11-30 21:50:21 +00:00
Rhys Perry
10ba06960f ac/nir: ignore 8/16-bit global access offset 
This was found by inspection, I'm not sure it can even happen.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26402>
 2023-11-30 21:50:21 +00:00
Boyuan Zhang
d07517d19f radeonsi: add new interface to handle multi slice reflist 
Add new flag and buffer to handle multi slice reflist case for hevc.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26081>
 2023-11-30 08:39:31 -05:00
Bas Nieuwenhuizen
748b7f80ef radv: Move sparse binding into a dedicated queue. 
1) This better reflects the reality that we only have one timeline
   of sparse binding changes.

2) Allows making it a threaded queue from the start in prep of
   explicit sync stuff.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16935>
 2023-11-29 17:37:37 +00:00
Bas Nieuwenhuizen
00faefa08e radv: Remove the sparse binding queue from coherent images. 
Never access the image on the queue family, so no need.

(Technically not sure if this is needed for Vulkan, somewhat of
 a backstop in case apps do it)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16935>
 2023-11-29 17:37:37 +00:00
Bas Nieuwenhuizen
6ff98f9313 radv: Add implementation of cmd buffers for a sparse binding queue. 
None of the commands are allowed on these ...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16935>
 2023-11-29 17:37:37 +00:00
Alyssa Rosenzweig
d50d9eccad ac,radv,radeonsi: use common 1D texture lowering 
It was pulled from ac.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26397>
 2023-11-29 14:04:15 +00:00
Konstantin Seurer
11897376c7 radv/rt: Skip null checks for small case counts 
The individual cases make sure the sbt_idx is not null implicitly
because the handles are always != 0.

Totals from 60 (22.56% of 266) affected shaders:
Instrs: 47841 -> 47655 (-0.39%)
CodeSize: 255028 -> 253460 (-0.61%)
Latency: 1179658 -> 1225311 (+3.87%); split: -0.02%, +3.89%
InvThroughput: 224122 -> 232851 (+3.89%); split: -0.02%, +3.92%
Copies: 12049 -> 12043 (-0.05%); split: -0.37%, +0.32%
Branches: 3312 -> 3290 (-0.66%)
PreSGPRs: 3494 -> 3472 (-0.63%)

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25089>
 2023-11-28 22:58:35 +00:00
Konstantin Seurer
fe674f67b1 radv/rt: Use a helper for inlining non-recursive stages 
So we don't have to write the same logic multiple times.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25089>
 2023-11-28 22:58:35 +00:00
Samuel Pitoiset
02ef01fa95 radv: enable DGC preprocessing for IBO 
This seems to improve performance for Starfield by +1% and Halo Infinite
by +15%!

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10025
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
 2023-11-28 14:07:37 +00:00
Samuel Pitoiset
e59a16bbb8 radv: use an indirect draw when IBO isn't updated as part of DGC 
To remove the dependency on the cmd buffer state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
 2023-11-28 14:07:37 +00:00
Samuel Pitoiset
2807e27231 radv: set the stream VA for DGC graphics 
This will be used to emit indirect draws when needed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
 2023-11-28 14:07:37 +00:00
Samuel Pitoiset
88bbdfd23e radv: remove useless NIR instructions when emitting IBO with DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
 2023-11-28 14:07:37 +00:00
Georg Lehmann
4b9618ceec aco: add test for post-ra DPP clobbered in linear cfg 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26373>
 2023-11-28 12:48:56 +00:00