Commit graph

78176 commits

Author SHA1 Message Date
Jason Ekstrand
768bd7f272 Merge commit '8b0fb1c152fe191768953aa8c77b89034a377f83' into vulkan
This pulls in Rob Clark's const_index changes for NIR
2016-02-09 15:30:39 -08:00
Rob Clark
8b0fb1c152 freedreno/ir3: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-02-09 17:30:33 -05:00
Rob Clark
ced8d3e773 nir: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-02-09 17:30:33 -05:00
Rob Clark
6921762de6 ptn: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-02-09 17:30:33 -05:00
Rob Clark
ead05e8670 ttn: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-02-09 17:30:33 -05:00
Rob Clark
b1770235ed ttn: small logic cleanup
The only case where dim!=NULL is where op==load_ubo.  But using
op==load_ubo is less confusing.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-02-09 17:30:33 -05:00
Rob Clark
b6cf98bc82 gtn: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-02-09 17:30:33 -05:00
Rob Clark
1df3ecc1b8 nir: const_index helpers
Direct access to intr->const_index[n], where different slots have
different meanings, is somewhat confusing.

Instead, let's put some extra info in nir_intrinsic_infos[] about which
slots map to what, and add some get/set helpers.  The helpers validate
that the field being accessed (base/writemask/etc) is applicable for the
intrinsic opc, for some extra safety.  And nir_print can use this to
dump out decoded const_index fields.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-02-09 17:30:33 -05:00
Chad Versace
4c5dcccfba anv/image: Fix usage for depthstencil images
The tests assertion-failed in vkCmdClearDepthStencilImage because the
isl surface lacked ISL_SURF_USAGE_DEPTH_BIT.

Fixes: https://gitlab.khronos.org/vulkan/mesa/issues/26
Fixes: dEQP-VK.pipeline.timestamp.transfer_tests.host_stage_with_clear_depth_stencil_image_method
Fixes: dEQP-VK.pipeline.timestamp.transfer_tests.transfer_stage_with_clear_depth_stencil_image_method
2016-02-09 12:54:30 -08:00
Chad Versace
c5e521f391 anv/image: Refactor choose_isl_surf_usage()
- Rename local var isl_flags -> isl_usage.
- Fix comment.
2016-02-09 12:54:30 -08:00
Chad Versace
2f4bb00c2b anv/image: Fix choose_isl_surf_usage()
Don't translate VkImageCreateInfo::usage into an isl_surf_usage bitmask.
Instead, translate anv_image::usage, which is a superset of
VkImageCreateInfo::usage.

For-Issue: https://gitlab.khronos.org/vulkan/mesa/issues/26
2016-02-09 12:54:04 -08:00
Kenneth Graunke
8b0f6de73d glsl: Disallow transform feedback varyings with compute shaders.
If the only stage is MESA_SHADER_COMPUTE, we should complain that
there's nothing coming out of the geometry shader stage just as
we would if the first stage were MESA_SHADER_FRAGMENT.

Also, it's valid for tessellation shaders to be the stage producing
transform feedback varyings, so mention those in the compiler error.

Found by inspection.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-02-09 12:34:11 -08:00
Marek Olšák
329181ae33 radeonsi: enable denorms for 64-bit and 16-bit floats
This fixes FP16 conversion instructions for VI, which has 16-bit floats,
but not SI & CI, which can't disable denorms for those instructions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
17fe3fa312 gallium: pass the robust buffer access context flag to drivers
radeonsi will not do bounds checking for loads if this is not set.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
d611fce23d gallium/radeon: add a function for adding llvm function attributes
This will be used for setting the new InitialPSInputAddr attribute.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
de2e28366a radeonsi: compile geometry shaders immediately
they have only 1 variant

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
f7a8b6fff5 radeonsi: split out code for deleting si_shader
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
e21142087c radeonsi: move code writing tess factors into a separate function
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
dc5fc3c2f6 radeonsi: make LLVM IR dumping less messy
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
c1041366db radeonsi: move a few r600_can_dump_shader calls to where they're needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
b6d5666fbf radeonsi: remove useless code that handles dx10_clamp_mode
"enable-no-nans-fp-math" is a wrong string and there was a disagreement
about fixing it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
57271d5364 radeonsi: dump SPI_PS_INPUT values along with shader stats
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
5a53628f45 radeonsi: read SPI_PS_INPUT_ADDR from LLVM if it returns it
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
9483fcc7f2 radeonsi: don't force gl_SampleMaskIn to 1 for smoothing
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
c379c2540b radeonsi: split PS input interpolation code into its own function
This will be used by the fragment shader prolog.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
b9126dcda8 radeonsi: implement forcing per-sample_interpolation using the shader key only
It was partly a state and partly emulated by shader code, but since we want
to do this in a fragment shader prolog, we need to put it into the shader
key, which will be used to generate the prolog.

This also removes the spi_ps_input states and moves the registers
to the PS state.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
4596f3c1b8 radeonsi: remove si_shader::ps_input_interpolate
tgsi_shader_info has this too.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
6dda2455c8 radeonsi: move BCOLOR PS input locations after all other inputs
BCOLOR inputs were immediately after COLOR inputs. Thus, all following inputs
were offset by 1 if color_two_side was enabled, and not offset if it was not
enabled, which is a variation that's problematic if we want to have 1 variant
per shader and the variant doesn't care about color_two_side (that should be
handled by other bytecode attached at the beginning).

Instead, move BCOLOR inputs after all other inputs, so BCOLOR0 is at location
"num_inputs" if it's present. BCOLOR1 is next.

This also allows removing si_shader::nparam and
si_shader::ps_input_param_offset, which are useless now.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
606e4185f3 radeonsi: move SPI_PS_INPUT_CNTL value computation to a separate function
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
90cbbe1c12 radeonsi: generate a color_two_side variant only if the shader reads colors
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
4bbbaaf191 radeonsi: move si_shader_context initialization into a separate function
This will be re-used later.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
a3e9a5f9f8 st/mesa: remove st_is_program_native
The default scenario sets GL_TRUE too.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-02-09 21:19:51 +01:00
Marek Olšák
7046c588eb st/mesa: unify destroy_program_variants cases for TCS, TES, GS
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-02-09 21:19:50 +01:00
Marek Olšák
75be3ee9f9 st/mesa: unify get_variant functions for TCS, TES, GS
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-02-09 21:19:50 +01:00
Marek Olšák
b8d31fdedf st/mesa: unify variants and delete functions for TCS, TES, GS
no difference between those

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-02-09 21:19:50 +01:00
Chad Versace
bdab29a312 isl: Add more assertions to isl_surf_get_depth_format()
R16_UNORM and R32_FLOAT are illegal formats for interleaved depthstencil
surfaces.
2016-02-09 11:40:08 -08:00
Jason Ekstrand
1d65abfa58 nir/spirv: Better handle constant offsets in texture lookups 2016-02-09 10:29:05 -08:00
Jason Ekstrand
209820739b nir/spirv: Set the vtn_mode and interface type for sampler parameters 2016-02-09 10:29:05 -08:00
Jason Ekstrand
de6c9c5f2e nir/inline_functions: Don't shadown variables when it isn't needed
Previously, in order to get things working, we just always shadowed
variables.  Now, we rewrite derefs whenever it's safe to do so and only
shadow if we have an in or out variable that we write or read to
respectively.
2016-02-09 10:29:05 -08:00
Jason Ekstrand
b6c00bfb03 nir: Rework function parameters 2016-02-09 10:29:05 -08:00
Jason Ekstrand
a485567d3a anv/WSI/X11: Use the right allocator for freeing swapchains 2016-02-09 10:29:05 -08:00
Brian Paul
fe14110f35 mesa: fix incorrect viewport position when GL_CLIP_ORIGIN = GL_LOWER_LEFT
Ilia Mirkin found/fixed the mistake.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93813
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-02-09 11:27:48 -07:00
Brian Paul
0193e20df5 mesa: rewrite save_CallLists() code
When glCallLists() is compiled into a display list, preserve the call
as a single glCallLists rather than 'n' glCallList calls.  This will
matter for an upcoming display list optimization project.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-02-09 11:27:48 -07:00
Brian Paul
711d5347cf mesa: add missing error check in _mesa_CallLists()
Generate GL_INVALID_VALUE if n < 0.  Return early if n==0 or lists==NULL.

v2: fix formatting, also check for lists==NULL.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-02-09 11:27:48 -07:00
Brian Paul
b1ddc03633 mesa: whitespace clean-ups in dlist.h
And remove 'extern' qualifiers.
2016-02-09 11:27:48 -07:00
Brian Paul
7d18faf8e7 st/mesa: don't allocate bitmap drawing state until needed
Most apps don't use glBitmap so don't allocate the bitmap cache or
gallium state objects/shaders/etc until the first call to st_Bitmap().

v2: simplify a conditional, per Gustaw Smolarczyk.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 11:27:48 -07:00
Brian Paul
a5799de3dc st/mesa: move the setup_bitmap_vertex_data() code into draw_bitmap_quad()
Now all the code to setup the vertex data and draw it is in one place.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 11:27:48 -07:00
Brian Paul
130d34ce65 st/mesa: refactor some bitmap drawing code
Move setup/restoration of rendering state into helper functions.
This makes the draw_bitmap_quad() function much more concise.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-09 11:27:47 -07:00
Chad Versace
e6d3432c81 anv: Replace anv_format::depth_format with ::has_depth
isl now understands depth formats. We no longer need depth formats in
the anv_format table.
2016-02-09 10:02:50 -08:00
Chad Versace
0a93067993 isl: Add func isl_surf_get_depth_format()
For depth surfaces, it gets the value for
3DSTATE_DEPTH_BUFFER.SurfaceFormat.
2016-02-09 10:02:50 -08:00