Commit graph

7732 commits

Author SHA1 Message Date
Mark Janes
4f86a70599 intel/fs: Lower DW untyped r/w messages to LSC when available
This puts the basic infrastructure in place for lowering logical
dataport messages to LSC messages.  We start with the two most obvious
opcodes and add more in later patches.

v2 (Sagar Ghuge):
 - Pass required params to message desc
 - Remove duplicate mlen calculation
 - Change commit message.

v3 (Jason Ekstrand):
 - Drop TGM support

Co-authored-by: Jason Ekstrand <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
2021-06-30 16:17:18 +00:00
Mark Janes
32ec0662fd intel/compiler: Add LSC messages to brw_schedule_instructions
v2 (Jason Ekstrand):
 - Use lsc_msg_desc_opcode()
 - Drop all opcodes for now and add them in later patches.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
2021-06-30 16:17:18 +00:00
Jason Ekstrand
8d3468ad5b intel/compiler: Add LSC to messages brw_ir_performance
This adds framework only.  No opcodes.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
2021-06-30 16:17:18 +00:00
Sagar Ghuge
634925694d intel/disasm: Disassemble LSC message extended descriptors
v2 (Mark Janes):
 - changed to lsc convention

v3 (Jason Ekstrand):
 - Use lsc_msg_desc_addr_type

Co-authored-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
2021-06-30 16:17:18 +00:00
Sagar Ghuge
2605727a80 intel/disasm: Disassmeble LSC messages
v2 (Jordan Justen):
 - Use PRIu64

v3 (Jason Ekstrand):
 - Drop ranged fence ops, Jason

v4: (Mark Janes)
 - fixed missing parameter to brw_message_desc_cmask_or_vector
 - changed to use lsc methods to extract fields

v5 (Jason Ekstrand):
 - Squash original disassembler patch and fixes togetherk
 - Use lsc_opcode_has_cmask
 - Prefix atomic ops with "atomic_"

Co-authored-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
2021-06-30 16:17:18 +00:00
Mark Janes
f5541cd4e9 intel/compiler: Add getter helpers for LSC message descriptor fields
v2: (Sagar Ghuge):
 - rename addr_reg_size to src0_len to match with bspec

v3 (Jason Ekstrand):
 - Re-arrange things in increasing bit order

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
2021-06-30 16:17:18 +00:00
Sagar Ghuge
4ff00194b7 intel/compiler: Add helpers for LSC message descriptors
v2 (Jason Ekstrand):
 - Squash all the similar patches together
 - Re-arrange and rename some things to be more consistent
 - Add a lsc_opcode_has_cmask helper
 - Drop is_one_addr_reg

v3 (Jason Ekstrand):
 - Add transpose
 - Re-order arguments to make more logical sense
 - Switch from `write` to `has_dest`

Co-authored-by: Mark Janes <mark.a.janes@intel.com>
Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
2021-06-30 16:17:18 +00:00
Sagar Ghuge
b67f1ff465 intel/compiler: Add support for LSC fence operations
v2 (Jason Ekstrand):
 - Squash SLM and global fence ops together

v3 (Jason Ekstrand):
 - Rework to use message descriptors instead of instruction fields

v4 (Jason Ekstrand):
 - Don't pass BTI into back-end emit function.  Always use FLAT.

Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
2021-06-30 16:17:18 +00:00
Sagar Ghuge
cf612e4dc1 intel/compiler: Define new LSC data port encodings
Xe-HPG comes with a massively reworked dataport.  The new thing, called
Load/Store Cache or LSC, has a significantly improved interface.
Instead of bespoke messages for every case, there's basically one or two
messages with different bits to control things like address size, how
much data is read/written, etc.  It's way nicer but also means we get to
rewrite all our dataport encoding/decoding code.  This patch kicks off
the party with all of the new enums.

v2 (Jason Ekstrand, Mark Janes):
 - Rename to LSC

v3 (Jason Ekstrand):
 - Add numbers to all enums

Co-authored-by: Mark Janes <mark.a.janes@intel.com>
Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
2021-06-30 16:17:18 +00:00
Jason Ekstrand
4a85a5e09f intel/devinfo: Add a has_lsc bit
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
2021-06-30 16:17:18 +00:00
Marcin Ślusarz
7048a15485 anv: drop unused argument of anv_descriptor_set_address
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11577>
2021-06-30 08:41:41 +00:00
Marcin Ślusarz
904bd8f358 anv: handle push descriptor sets when they are sent with push constants
When vkCmdPushDescriptorSetKHR is used, the descriptor set is allocated
internally without belonging to any pool. Such descriptor set will be
visible on the GPU side because it's a part of the dynamic state stream,
but we still have to store its address in the array of descriptor sets.

Complements: 379b9bb7b0 ("anv: Support fetching descriptor addresses from push constants")

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11577>
2021-06-30 08:41:41 +00:00
Marcin Ślusarz
79a50c6f54 anv: keep descriptor set's address directly in anv_descriptor_set
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11577>
2021-06-30 08:41:41 +00:00
Emma Anholt
b18cf54f0d intel: Early exit from inst_is_in_block().
Surely the compiler would sort that out, you would think.  But no, my
debugoptimized build improves
dEQP-GLES31.functional.ubo.random.all_per_block_buffers.13 runtime by 25%
on my SKL from this change.

This was the slowest test in the GLES31 tests on APL in CI, at 22s.  And
yes, we were spending around half of our runtime in this function.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11631>
2021-06-29 16:48:40 +00:00
Lionel Landwerlin
71b7c7b0dc intel/perf: use the right popcount for 64bits
We're currently using the 32bit version which is dropping half the
bits of the 64bits values.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11607>
2021-06-29 06:29:53 +00:00
Eleni Maria Stea
e094f75bd0 intel: PAGE_SIZE used in allocators shouldn't be defined on FreeBSD
iris, i965, and anv define the PAGE_SIZE in anv_allocator and bufmgr
files. As on FreeBSD the page size is defined in machine/param.h that is
indirectly included by those files, we'd rather define it only when the
system is not FreeBSD to avoid compile errors.

v2: Changed the path in the comment to make clear that machine/params.h
is a FreeBSD system file.

Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11203>
2021-06-28 21:12:24 +03:00
Ella-0
86fe8db4aa anv: expose primary node to VK_EXT_physical_device_drm even when VK_KHR_display is not enabled
Fixes: e9e1e0362b ("anv: implement VK_EXT_physical_device_drm")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11616>
2021-06-28 14:03:22 +00:00
Marcin Ślusarz
2cf189cc88 intel/fs: use stack for temporary array
"regs" is an array of 2 ->
  "m" must be <= 2 ->
  "components" array can be allocated on the stack

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11575>
2021-06-28 09:44:40 +00:00
Marcin Ślusarz
5c66fb7e6e intel/blorp: initialize BLEND_STATE using braced initializer list
Coverity complains that memset has no effect, because of size 0.
Size of BLEND_STATE struct is 0 on gfx [6, 7.5], so memset has
nothing to do there. This is of course harmless, but we can make
code simpler by replacing memset with an empty initializer list
and at the same time avoid a warning from Coverity.

CID: 1486015

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11574>
2021-06-28 09:31:41 +00:00
Marcin Ślusarz
5c5423e6ee intel/tools: fix potential memory leaks
CID: 1444041
CID: 1444104

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11574>
2021-06-28 09:31:41 +00:00
Marcin Ślusarz
14227b3364 intel/tools: fix invalid type in argument to printf format specifier
Also mark parse_error as printf-like to catch such errors with gcc.

CID: 1473100
CID: 1473101

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11574>
2021-06-28 09:31:41 +00:00
Marcin Ślusarz
f2a3c9de67 intel/tools: fix int-to-pointer/pointer-to-int cast warnings on 32-bit
gcc complains:
../src/intel/tools/aub_write.c: In function ‘populate_ppgtt_table’:
../src/intel/tools/aub_write.c:254:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  254 |                (void *)(aub->phys_addrs_allocator++ << 12);
      |                ^
../src/intel/tools/aub_write.c:258:27: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
  258 |                        i, (uint64_t)table->subtables[i]);
      |                           ^
../src/intel/tools/aub_write.c:273:24: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
  273 |          (level == 1 ? (uint64_t)table->subtables[i] :
      |                        ^
../src/intel/tools/aub_write.c: In function ‘ppgtt_lookup’:
../src/intel/tools/aub_write.c:346:11: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
  346 |    return (uint64_t)L1_table(ppgtt_addr)->subtables[L1_index(ppgtt_addr)];
      |           ^
../src/intel/tools/intel_sanitize_gpu.c: In function ‘bo_size’:
../src/intel/tools/intel_sanitize_gpu.c:99:15: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
   99 |    return e ? (uint64_t)e->data : UINT64_MAX;
      |               ^

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11574>
2021-06-28 09:31:41 +00:00
Marcin Ślusarz
53c49ce41f intel/tools: fix left shift overflow on 32-bit
gcc complains:
../src/intel/tools/aub_write.c:394:53: warning: left shift count >= width of type [-Wshift-count-overflow]
  394 |    assert((aub->phys_addrs_allocator + size) < (1UL << 32));
      |                                                     ^~

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11574>
2021-06-28 09:31:41 +00:00
Marcin Ślusarz
d19cf7d572 anv: fix potential integer overflows
In all cases both variables has a type of uint32_t, so multiplying
them will also generate uint32_t. The results of those multiplications
are used as uint64_t's, so Coverity thinks there might be integer
overflows here.
I don't think it's possible to hit them (query BOs should be relatively
small), but let's avoid those overflows.

CID: 1472820
CID: 1472821
CID: 1472822
CID: 1472824
CID: 1475934
CID: 1475927

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11574>
2021-06-28 09:31:41 +00:00
Marcin Ślusarz
365c7cc87c intel/decoder: add assert for register size
Coverity complains about out-of-bounds access in
intel_field_iterator_init, because it doesn't know that the GT_MODE
register has a size of 4 bytes. Add an assertion to verify that.

CID: 1474552

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11574>
2021-06-28 09:31:41 +00:00
Lionel Landwerlin
40b67a2922 anv: allocate bigger batches as we grow command buffers
This is the first time we see an application running out of mmap().

We essentially allocate too many batches (+65k) and end up not being
able to mmap them, at which point we can't mmap anything anymore and
things go sideways.

This change allocates bigger batch BOs as we grow an existing command
buffer. This drastically reduces the number of BOs we need to allocate
(the benchmark that reported the issue now reaches a max of ~630 BOs,
instead of reaching 65k and failing previously).

v2: Track the total batch size of command buffers (Jason)
    Just give 0 for batch_len to i915 (Jason)

v3: Fix indentation (Jason)

v4: Drop uncessary reshuffling of error labels (Jason)

v5: Remove empty lines (Marcin)

v6: Limit BO growing to chunks of 16Mb (Jason)

v7: Add assert on initial size (Jason)

v8: Add define for max size (Jason)

v9: Fixup v7 assert for non softpin platforms (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4956
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11482>
2021-06-26 12:23:54 +03:00
Caio Marcelo de Oliveira Filho
5853f17c30 anv: Advertise VK_KHR_shader_subgroup_uniform_control_flow
This is always valid for Intel, so we don't need to do anything
different if the Execution Mode is being used.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11476>
2021-06-25 22:41:32 +00:00
Mike Blumenkrantz
6a79ee97f4 anv: VK_EXT_multi_draw implementation
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11531>
2021-06-25 17:16:14 +00:00
Mike Blumenkrantz
1e39f2c199 anv: unify some draw state vertex constant emission
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11531>
2021-06-25 17:16:14 +00:00
Samuel Iglesias Gonsálvez
e791b2045a anv: do not dereference VkPipelineMultisampleStateCreateInfo always
VkGraphicsPipelineCreateInfo.pMultisampleState is a pointer to a
VkPipelineMultisampleStateCreateInfo structure, and is ignored if the
pipeline has rasterization disabled.

Fixes a crash in one CTS tests that checks this.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11601>
2021-06-25 14:42:42 +00:00
Jason Ekstrand
63e80d441a intel/genxml: Remove old scratch fields on GFX version 12.5
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
2021-06-25 00:18:29 +00:00
Jason Ekstrand
eeeea5cb87 anv: Add support for scratch on XeHP
Rework:
 * Jordan: Handle per_thread_scratch==0 in anv_scratch_pool_get_surf
 * Jordan: Update subslices in anv_scratch_pool_alloc
 * Jason: Clean up the patch a bit

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
2021-06-25 00:18:29 +00:00
Jason Ekstrand
8ca0513eca intel/genxml: Add new ScratchSpaceBuffer fields on GFX version 12.5
Rework:
 * Jordan: Fix MEMZONE_BINDER_START detection
 * Jordan: Bump the IRIS_BINDLESS_SIZE to 8M

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
2021-06-25 00:18:29 +00:00
Jason Ekstrand
1e242785c3 intel/fs: Implement load/store_scratch on XeHP
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
2021-06-25 00:18:29 +00:00
Jason Ekstrand
c38812be1d intel/fs: Implement spilling on XeHP
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
2021-06-25 00:18:29 +00:00
Jason Ekstrand
96ee78778b intel/isl: Add support for scratch buffers
XeHP adds support for a new surface type for scratch.  It's similar to
SURFTYPE_STRBUF in that it's a 2D array-of-struct format but the one
key difference is that the U coordinate is computed automatically based
on the thread ID and only the V coordinate is provided in the dataport
message.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
2021-06-25 00:18:29 +00:00
Jason Ekstrand
443627fcc0 intel/genxml: Add SURFTYPE_SCRATCH on GFX version 12.5
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
2021-06-25 00:18:29 +00:00
Jason Ekstrand
d31dd81292 anv: Claim to be a discrete GPU if has_lmem
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>
2021-06-24 16:14:38 +00:00
Jordan Justen
b6a1063c2e intel/dev: Set has_local_mem for DG1
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>
2021-06-24 16:14:38 +00:00
Sagar Ghuge
e505c221fa anv: Allocate scratch and workaround BO in local memory
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>
2021-06-24 16:14:38 +00:00
Sagar Ghuge
6352371ff6 anv: Allocate BO in appropriate region
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>
2021-06-24 16:14:38 +00:00
Sagar Ghuge
3f8eca7f82 anv: Wrapper around I915_GEM_CREATE_EXT_MEMORY_REGIONS
v2 (Jordan Justin):
 - add anv_gem_stubs.c impl

v3 (Jason Ekstrand):
 - Use the upstream uAPI
 - Rework the interface a bit

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>
2021-06-24 16:14:38 +00:00
Sagar Ghuge
65e8d72bc1 anv: Query memory region info
Create additional memory type with DEVICE_LOCAL_BIT if we have local
memory region aviable.

v2 (Jason Ekstrand):
 - Don't leak mem_regions if the second ioctl fails

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>
2021-06-24 16:14:38 +00:00
Jordan Justen
cb6feae0b5 intel/devinfo: Add has_local_mem
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>
2021-06-24 16:14:38 +00:00
Jason Ekstrand
b8030ab1ea isl,docs: Add a chapter on AUX state tracking
We also update and improve the docs in isl.h which get pulled into this
new chapter.

Acked-by: Luis Strano <luis.strano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>
2021-06-24 13:57:40 +00:00
Jason Ekstrand
94a52bc85c isl,iris: Move the extra_aux_surf logic into iris
This gets rid of the awkward interface for isl_surf_get_ccs_surf where
we passed it two aux surfaces and it was supposed to fill out the second
one based on whether or not the first one already had stuff in it.
Instead, we now pass it three well-labled surfaces: surf,
hiz_or_mcs_surf, and ccs_surf which have obvious meanings.  This does
mean that iris has to carry a bit of logic and we have to flip
parameters around in all the callers.  But the resulting interface is
much cleaner.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>
2021-06-24 13:57:40 +00:00
Jason Ekstrand
37f76aab1c isl: Take a hiz_or_mcs_surf in isl_surf_supports_ccs
Whether or not a surface supports CCS on Tigerlake and later is
dependent not only on the main surface but also on the MCS or HiZ
surface, if any.  We were doing some of these checks in
isl_get_ccs_surf based on the extra_aux parameter but not as many as we
probably should.  In particular, we were really only checking HiZ
conditions and nothing for MCS.  It also meant that, in spite of the
symmetry in names, the checks in isl_surf_get_ccs_surf were more
complete than in isl_surf_supports_ccs.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>
2021-06-24 13:57:40 +00:00
Jason Ekstrand
2d2590a879 isl: Assert some iris invariants in isl_surf_get_ccs_surf
The only driver which calls isl_surf_get_ccs_surf with extra_aux != NULL
is iris and it always calls it with two aux surfaces and never calls it
for CCS twice.  We can turn those checks into asserts.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>
2021-06-24 13:57:40 +00:00
Dave Airlie
0acd202858 intel/genxml: fix gfx6 GS SVB_INDEX encoding
This seems to match what the docs + 965 traces say

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>
2021-06-24 06:50:49 +00:00
Tapani Pälli
55951ac28e anv: fix emitting dynamic primitive topology
Initial implementation missed various fields that derive from the
primitive topology. This patch fixes 3DSTATE_RASTER/3DSTATE_SF,
3DSTATE_CLIP and 3DSTATE_WM (gen7.x) emission in the dynamic case.

Fixes: f6fa4a8000 ("anv: add support for dynamic primitive topology change")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4924
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11379>
2021-06-23 12:01:45 +00:00