Cooper Yuan
5ff3368c1f
R6xx, add edge rules for triangles
2009-05-28 16:51:49 -04:00
Corbin Simpson
b70fcd620d
r300-gallium, radeon-gallium: Make add_buffer indicate when a flush is needed.
...
On a side note, why is RADEON_MAX_BOS 24? Should ask airlied about that.
2009-05-28 07:46:34 -07:00
Jerome Glisse
5dcbcbfca4
r300: when using cs path emit scissor in the cmdbuffer
2009-05-28 13:48:38 +02:00
Jerome Glisse
2f9189d538
r300: rework texture offset emission.
2009-05-28 11:40:58 +02:00
Ben Skeggs
534f1e8f02
nv50: some mipmapping fixes
2009-05-28 16:06:25 +10:00
Christoph Bumiller
c11c107f7d
nv50: negate sources directly where supported
2009-05-28 16:06:25 +10:00
Christoph Bumiller
87eea6e2b2
nv50: introduce emit_cvt and use it
...
This makes some code cleaner, and we can now easily
do CEIL and TRUNC.
2009-05-28 16:06:24 +10:00
Christoph Bumiller
3accd7ebe9
nv50: fix TXP
...
For TXP we need to divide texture coords by their w component, or
use the coords' 1/w in the perspective interpolation instruction.
This also tries to support 1D, 3D and CUBE textures, and lets the
instruction only load the components that are used.
2009-05-28 16:06:24 +10:00
Christoph Bumiller
94ba165dff
nv50: use multiple constant buffers
...
Use different buffers for immds, FP params, and VP params.
One has to map constant buffer indices in shader code to buffers
defined via CB_DEF. In principle, we could use more buffers so
we'd have to change the shader code less frequently.
2009-05-28 16:06:24 +10:00
Christoph Bumiller
f9268ccd7f
nv50: don't look for unfreed temps in free_nv50_pc
...
Since we stopped using alloc_temp to get hw indices for FP attrs
there shouldn't be any non-deallocated temps left.
2009-05-28 16:06:23 +10:00
Christoph Bumiller
7ab96f4f73
nv50: release hw TEMPs early
...
Since we know when we don't use a TEMP or FP ATTR register anymore,
we can release their hw resources early.
2009-05-28 16:06:23 +10:00
Christoph Bumiller
708c711f83
nv50: allow immediates for MOV, ADD and MUL
...
Immediates are inlined now where possible, so we need to set
pc->allow32 to FALSE in LIT where we have the conditional MOV,
since immediates swallow the predicate bits.
2009-05-28 16:06:22 +10:00
Christoph Bumiller
d015cba88f
nv50: enable half insns for MOV and MUL
2009-05-28 16:06:22 +10:00
Christoph Bumiller
44b3bfaa75
nv50: make sure half-long insns are paired
...
I chose to just convert unpaired 32 bit length instructions
after parsing all instructions, although it might be possible
to determine beforehand whether there would be any lone ones,
and then even do some swapping to bring them together ...
2009-05-28 16:06:21 +10:00
Christoph Bumiller
de651a228f
nv50: enable KIL in register 19a8
2009-05-28 16:06:21 +10:00
Christoph Bumiller
dac709d0cf
nv50: don't overwrite sources before they're used
...
This would have happened in p.e. ADD TEMP[0], TEMP[0].xyxy, TEMP[1]
or RCP/RSQ TEMP[i], TEMP[i].
2009-05-28 16:06:21 +10:00
Christoph Bumiller
f579a99cc6
nv50: put FP outputs where they belong
...
Depth output in fragment programs should end up in the first
register after the color outputs.
2009-05-28 16:06:20 +10:00
Christoph Bumiller
dd9ded42b9
nv50: modified FP attribute loading
...
VP outputs that should be loadable in the FP are mapped to
interpolant indices by HPOS, COL0 etc.; of course HPOS is
always written, so the highest byte of 1988 is a bitmask that
selects which components of HPOS are used for interpolants,
i.e. the FP inputs in COL0 start at index POPCNT(1988[24:28]).
2009-05-28 16:06:19 +10:00
Christoph Bumiller
e88ec312df
nv50: inspect decl semantic and interpolation mode
...
Record interpolation mode for attributes while parsing declarations,
and also remember the indices of FP color inputs and FP depth output,
which has to end up in the highest output register.
2009-05-28 16:06:19 +10:00
Christoph Bumiller
bcecb8ff66
nv50: record last access to temp and attr regs
...
We now inspect the TGSI instructions in tx_prep to determine where
temps and FP attrs are last accessed.
This will enable us to reclaim some temporaries early and we also
use it to omit pre-loading FP attributes that aren't used.
2009-05-28 16:06:18 +10:00
Christoph Bumiller
7e7d3a87ec
nv50: save some space in immediate buffer
...
We could do even better (like just allocating 1 value in alloc_immd),
but that's fine for now I guess.
2009-05-28 16:06:18 +10:00
Christoph Bumiller
aad31d69ce
nv50: fix SIGN_SET case in tgsi_src
2009-05-28 16:06:17 +10:00
Christoph Bumiller
4a7cf8f66f
nv50: set dst.z,w to 0,1 in SCS and XPD
...
According to tgsi-instruction-set.txt, if they are written, z and w
should be set to 0 and 1 respectively in SCS, and w to 1.0 in XPD.
2009-05-28 16:06:17 +10:00
Christoph Bumiller
229992d281
nv50: make LRP instruction nicer
2009-05-28 16:06:17 +10:00
Christoph Bumiller
9417582f39
nv50: fix some memory leaks in shader assembler
2009-05-28 16:06:16 +10:00
Ben Skeggs
65e3fb7b46
nouveau: explicitly request mappable buffers for the moment
2009-05-28 16:06:16 +10:00
Mike Kaplinksiy
713b636a0e
draw: Fix assertion failure at fetch_emit_prepare
2009-05-27 22:53:59 -07:00
Brian Paul
5be48307d5
demos: remove some old debug/test code
2009-05-27 19:37:32 -06:00
Brian Paul
b86067c610
softpipe: comments
2009-05-27 19:36:59 -06:00
Brian Paul
31deacb8d3
softpipe: include sp_winsys.h to silence warning (unprototyped function)
2009-05-27 19:30:07 -06:00
Brian Paul
5d75124db4
softpipe: fix flat shading provoking vertex for PIPE_PRIM_POLYGON
...
Use the first vertex, not the last.
2009-05-27 19:27:31 -06:00
Brian Paul
c13bd74885
st/mesa: init Format field of vertex arrays for feedback mode
...
Fixes segfault in glRasterPos()
2009-05-27 19:24:09 -06:00
Jerome Glisse
3a6dd3ebb3
radeon: emit scissor before emiting vertices
2009-05-27 21:50:03 +02:00
Jerome Glisse
6141c9ba71
radeon: emit scissor when using cs submission style.
2009-05-27 09:36:07 +02:00
Eric Anholt
8ec6e03679
i915: Fall back on NPOT textured metaops on 830-class.
2009-05-26 20:50:54 -07:00
Eric Anholt
0e83e8f51a
i915: Restore the Viewport and DepthRange functions on 8xx.
...
Fixes failed viewport updates on glxgears (and other apps) resize since
e41780fedc .
Bug #20473 .
2009-05-26 19:50:23 -07:00
Chris Wilson
9178b31546
intel: Override MaxRenderbufferSize with hardware constraints
...
Limit the maximum renderbuffer size to 8192 on i965 and to 2048 on
earlier hardware.
2009-05-26 15:51:33 -07:00
Alex Deucher
98bc311717
enable surface sync function
...
- needs to be more fine-grained
2009-05-26 14:30:26 -04:00
Alex Deucher
f3eaba017c
r6xx: fix more r6xx specific cases
2009-05-26 12:21:54 -04:00
Alex Deucher
930b42693e
R6xx: select proper shader format
2009-05-26 11:36:55 -04:00
Alex Deucher
17417fc8ee
fix segfault when running glxinfo
2009-05-26 11:13:44 -04:00
Alex Deucher
4a28974cf5
add missing RS780 pci id
2009-05-26 10:44:44 -04:00
Alex Deucher
ced2f1b94c
fix build when HAVE_LIBDRM_RADEON is defined
2009-05-26 10:33:23 -04:00
Jerome Glisse
9dee2f20a2
radeon: on update drawable don't firevertices as it might be call from GetLock
...
To avoid locking bug we shouldn't not call firevertices from this path
as it's call from radeon get lock.
2009-05-25 16:05:45 +02:00
Jerome Glisse
714f5e689f
r200: emit scissor when dri2 is enabled
...
In DRI1 kernel emit scissor but in dri2 cs path we have to
explicitly program them.
2009-05-25 15:47:39 +02:00
Jerome Glisse
39ef33708c
r200: fix multitexturing in dri2 path
2009-05-25 13:17:22 +02:00
Jerome Glisse
80f1ac87f2
r200: emit cliprect with indexed primitive
2009-05-25 11:29:32 +02:00
Jerome Glisse
9b1efcb87c
radeon: realloc dma if needed after revalidate
...
Revalidate can trigger flushing and dma buffer deallocation,
so retry allocation on such case.
2009-05-24 16:24:53 +02:00
Nicolai Hähnle
7dd184dc4d
radeon: Remove drawable & readable from radeon_dri_mirror
...
The duplication of state data caused a crash due to double-free on destruction
of context, because a variable wasn't correctly null'ed out.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
2009-05-24 15:41:53 +02:00
Brian Paul
2d30dafadd
mesa: fix warning message in vbo_exec_DrawRangeElements()
2009-05-22 15:49:38 -06:00