There's only 1 sampler state behind
3DSTATE_SAMPLER_STATE_POINTERS[_VS|_HS|_DS|_GS|_PS] and
3DSTATE_SAMPLER_STATE_POINTERS.[PointertoVSSamplerState|PointertoPSSamplerState|PointertoGSSamplerState].
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
state_addr == bo.addr, bo.size==0 is handled by another check
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
Context batches tend to have a lot of multi-LRI and, if we want to be
able to parse those registers nicely, we really handle it.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
I chose to drop "HW" from the name of this field because on Gen11
it applies to both HW and SW binding tables, so it's a bit of a
misnomer.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
Instead of using tempfiles to communicate between child & parent
process. The latter sometimes resulted in hitting the meson timeout if
there was high filesystem pressure.
Fixes: ccaa5b034f "intel/tools: rewrite run-test.sh in python"
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9528>
Anvil can handle if this call fails, but not if we assert. :)
Reported-by: Brian Paul <brianp@vmware.com>
Fixes: 5d84c764fd ("anv: Gather engine info from i915 if available")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9664>
The messages for those 16-bit operations still use 32-bit sources and
destinations, so expand them accordingly when building the payload.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8750>
If we load constant data using pull constant SENDS, and we later load
that register with some other data, we can end up in a situation where
we don't track the initial fixed register write and therefore end up
using uninitialized registers.
This tracks write-on-write of fixed GRFs like we do for normal virtual
GRFs.
v2: Fix post_alloc_reg case (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9667>
This makes UBO loads in the variable pointers or bindless case work just
like SSBO loads in the sense that they use A64 messages and 64-bit
global addresses. The primary difference is that we have an
optimization in anv_nir_lower_ubo_loads which uses a (possibly
predicated) block load message when the offset is constant so we get
roughly the same performance as we would from plumbing load_ubo all the
way to the back-end.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
Instead of load_global_constant_offset/bounded, we want to use the
Intel-specific block load intrinsic whenever we can. This way we get
the same wide block loads that we usually use for constant offset UBO
pulls with a binding table.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
This also means that some of the newly added helpers need to grow a bit
to support VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_DATA_EXT.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
This function has exactly two call sites. The first is where we had
these calculations before. The second only cares about the size of the
SSBO so all the extra code we emit will be dead. However, NIR should
easily clean that up and this lets us consolidate things a bit better.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
Instead of packing the descriptor offset into the packed portion, use
that unused channel we have lying around. This potentially allows for
larger descriptor sets. We also re-arrange the components a bit to make
it more like the 64bit_bounded_global memory address format.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
This has the advantage of giving us cheaper address calculations because
we can calculate in 32 bits first and then do a single 64x32 add. It
also lets us delete a bunch of code for dealing with descriptor
dereferences (vulkan_resource_reindex, and friends) because our bindless
SSBO pointers are now vec4s regardless of whether or not we're doing
bounds checking. This also unifies UBOs and SSBOs. The one down-side
is that, in certain variable pointers cases, it may end up burning more
memory and/or increasing register pressure. This seems like a worth-
while trade-off.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
Instead of doing the array check at the load_vulkan_resource_index
intrinsic, stuff it in the vec2 and handle it at load_vulkan_descriptor
time. This allows the bounds check to take any re-index intrinsics into
account. This only affects variablePointers + SSBOs + Gen7.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
We're about to enable bindless UBOs via A64 memory access like we do for
SSBOs. In order to prevent 100% of UBOs from hitting that path, we
enable them in the early lowering. This way we'll still get binding
table-based UBO access for any non-bindless ones. In particular, we
need this for UBO pushing to work.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
Rewrite them all to work on an index/offset vec2 instead of some only
returning the index. This means SSBO size handling is a tiny bit more
complicated but it will also mean we can use them for descriptor buffers
properly.
This also fixes a bug where we weren't bounds-checking re-index
intrinsics because we applied the bounds check at the tail of the
recursion and not at the beginning.
Fixes: 3cf78ec2bd "anv: Lower some SSBO operations in..."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
This makes things a bit more generic for use in the next commit.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
NIR can do a bit better job optimizing this version.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
This allows us to do bounds checked A64 block load without the it being
counted as control-flow by NIR. This means that NIR optimizations like
CSE will be able to work on these the same as a regular load.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
v2: link libvulkan_util with libglsl so it can find the glsl singleton symbols.
v3: link with libcompiler instead of libglsl (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> for the v3dv bits.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> for the turnip bits.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> for the radv bits.
Acked-by: Dave Airlie <airlied@redhat.com> for the lvp bits.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9457>
This gets rid of unused variable warnings on genX_thing, because
now the compiler will think that the unknown hardware generation
case is unreachable.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9634>
This should make both GCC and clang happy and make them believe that
the array bounds are not exceeded.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9634>
GEN_GEN and GEN_VERSIONx10 macros provide a consistent way to do platform
version checks. We can avoid platform specific macros.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9608>
Use GEN_VERSIONx10 == 75 check in place of GEN_IS_HASWELL macro.
GEN_GEN and GEN_VERSIONx10 macros provide a consistent way to do platform
version checks. We can avoid platform specific macros.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9608>
Otherwise, they look like booleans but, if you put a value other than
0/1 in them, the GenXML generator code will explode.
Fixes: b6875b0094 "anv: Drop has_slm in emit_l3_config for gen11+"
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9614>
We can use surface_count as it is to set binding table entry count since
it's already in units.
On Felix's Tigerlake with the GPU at fixed frequency, this patch
improves performance of several games:
- Shadow of the Tomb Raider: +1.5%
- Dota2vk: +1%
- Dark Souls: +1%
v2: (Ken)
- Remove get_binding_table_entry_count() and use surface_count directly.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9548>
