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Author SHA1 Message Date
Alyssa Rosenzweig
52fe998aa6 panfrost: Track preloaded registers 
We already collect this information. We may as well make use of it.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:40 +00:00
Alyssa Rosenzweig
e8566f7529 pan/indirect_draw: Support IDVS jobs 
Handle as tiler jobs with an extra vertex DCD at the end.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:40 +00:00
Alyssa Rosenzweig
37ab248c77 pan/indirect_draw: Split out update_dcd 
This is common between vertex/tiler jobs and needs to be duplicated for
IDVS jobs.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:40 +00:00
Alyssa Rosenzweig
d696183d4d pan/indirect_draw: Don't upload garbage UBO 
There should never be a CPU pointer in GPU memory, let's say that...

Fixes: 2e6d94c198 ("panfrost: Add helpers to support indirect draws")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
 2021-12-20 18:21:40 +00:00
Pierre-Eric Pelloux-Prayer
1cb5c1775b glx: fix querying GLX_FBCONFIG_ID for Window 
This commit fixes apps using the following sequence:
1. XCreateWindow(dpy) -> win
2. glXCreateContextAttribsARB(dpy, ...) -> ctx
3. glXMakeCurrent(dpy, win, ctx)
4. glXQueryDrawable(dpy, win, GLX_FBCONFIG_ID, ...)

glXQueryDrawable returned 0 (while correctly returning a valid
GLXFCONFIG_ID for other types of drawables).

This commit adds the same dance as driInferDrawableConfig to get
the GLX visual from the Window, and then the GLXFBCONFIG_ID of
this visual.

This fixes:
* piglit: glx-query-drawable --attr=GLX_FBCONFIG_ID --type=WINDOW
* Maya which uses the config ID from step 4 as an input to
glXChooseFBConfig.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14174>
 2021-12-16 01:21:36 +00:00
Alyssa Rosenzweig
d92e353a11 pan/mdg: Fix definition of UBO unpack 
Needed to link the disassembler separate from the rest of the compiler,
as in out-of-tree pandecode builds. Which I haven't done for Midgard in
well over a year, enough time for this to bit rot.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14185>
 2021-12-14 03:42:28 +00:00
Erico Nunes
013900c4d2 mesa: fix GL_MAX_SAMPLES with GLES2 
EXT_multisampled_render_to_texture on GLES2 allows the
GL_MAX_SAMPLES_EXT enum to be used.

Move the condition from the GLES3 section to the GLES2 one so
that it stops returning GL_INVALID_ENUM in that case.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13967>
 2021-12-11 01:31:59 +00:00
Dave Airlie
d051854cca treewide: drop mtypes/macros includes from main 
These aren't required in lots of places, so remove them.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14127>
 2021-12-08 22:14:45 +00:00
Manas Chaudhary
def254b05f panvk: Add check for null fence 
Signed-off-by: Manas Chaudhary <manas.chaudhary@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14108>
 2021-12-07 21:18:44 +00:00
Alyssa Rosenzweig
46b758cbcc pan/va: Add table parameter to LD_ATTR_IMM 
..and test the instruction.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14065>
 2021-12-06 23:06:59 +00:00
Alyssa Rosenzweig
a5084127eb pan/va: Add sample/update modes to LD_VAR 
..and test the new instructions. As usual, the semantics are the same as
bifrost, but the encoding is simpler.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14065>
 2021-12-06 23:06:59 +00:00
Alyssa Rosenzweig
3485e9dd3d pan/va: Make LD_VAR index more fine-grained 
Index in bytes instead of vec4s, since varyings on Valhall are no longer
vec4 based like on previous Malis.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14065>
 2021-12-06 23:06:59 +00:00
Alyssa Rosenzweig
7d157ae50e pan/va: Add more assembler tests 
For new patterns

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14065>
 2021-12-06 23:06:59 +00:00
Alyssa Rosenzweig
f3d4d074da pan/va: Disambiguate sign of CSEL instructions 
The naming scheme is a bit simpler than Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14065>
 2021-12-06 23:06:59 +00:00
Alyssa Rosenzweig
9da627fd6d pan/va: Improve assembler unit test output 
Instead of using Python hex() to print the result, print the result in
the same format as the disassembler for easy visual comparison. This
means we don't need to reprint the expectation. This gives output like:

   7c 7d 11 33 04 80 66 00    LD_ATTR_IMM.v4.f16.slot0 @r0:r1, `r60, `r61, index:0x1
   7c 7d 10 33 04 80 66 00    Incorrect assembly

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14065>
 2021-12-06 23:06:59 +00:00
Alyssa Rosenzweig
9b068f186a panfrost: Add Valhall support to pandecode 
Valhall v9 introduces a number of new data structures since Bifrost v7,
and removes a number of traditional data structures. Add decode routines
for the new Valhall data structures, and condition the old routines on
(PAN_ARCH <= 7) to remain buildable and warning-free.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14063>
 2021-12-06 20:46:09 +00:00
Alyssa Rosenzweig
745d7db748 panfrost: Don't shadow Mesa's fui() 
Will fix a compiler error when we #include the Valhall disassembler
header from pandecode.

Fixes: 688827f3c5 ("pan/va: Add disassembler generator")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14063>
 2021-12-06 20:46:09 +00:00
Alyssa Rosenzweig
244f3704d4 panfrost: Zero initialize disassembler stats 
Keep it simple for introducing new support.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14063>
 2021-12-06 20:46:09 +00:00
Alyssa Rosenzweig
96acad5cd5 panfrost: Add XML for Valhall data structures 
Fork the latest canonical XML (Bifrost v7) and adapt to the data
structures found in the earliest Valhall GPU I could get my hands on
(Valhall v9). This should minimize the churn needed for the port by
keeping the Valhall model close to the Bifrost we already supported.

It is not known what happened to v8. It appears to have been yeeted from
existence.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14063>
 2021-12-06 20:46:09 +00:00
Alyssa Rosenzweig
6eb0770be8 panfrost: Add "hex" type to GenXML 
Although known fields wouldn't be given the type "hex", it is useful as
the default type for unknown fields while reverse-engineering, and as
such is used in the Valhall XML.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14063>
 2021-12-06 20:46:09 +00:00
Alyssa Rosenzweig
72b3f21cd4 pan/va: Only hex dump when verbosely disassembling 
Closer behaviour to Bifrost, making the entrypoints symmetric.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14063>
 2021-12-06 20:46:09 +00:00
Alyssa Rosenzweig
7fa5382ad6 pan/bi: Link with Valhall disassembler 
For pandecode's use.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14063>
 2021-12-06 20:46:09 +00:00
Alyssa Rosenzweig
ae4d46d457 panfrost: Only build GPU indirect kernels for v7 
These kernels aren't tested (and are probably broken) elsewhere. Don't
waste cycles trying to compile for other architectures. This reduces the
amount of code that needs to be ported to a new architecture.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14064>
 2021-12-06 13:54:25 +00:00
Alyssa Rosenzweig
8d2be391e3 panfrost: Add empty tile flags to GenXML 
These flags control special CRC handling for empty tiles using the CRC
clear colour field added on Bifrost. Their use depends on CRC being
used. We missed these flags earlier; let's add them since they are used
by the Valhall DDK but are not new to Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13982>
 2021-11-30 15:43:59 +00:00
Ilia Mirkin
e31d08d307 ci: move windowoverlap exclusion to all-skips 
The test is just plain not built by our containers. Skip it everywhere.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13919>
 2021-11-29 18:08:49 -05:00
Alyssa Rosenzweig
c6ca2d1929 panfrost: Handle AFBC_FEATURES in drm-shim 
Fixes the warning with drm-shim:

   Unknown DRM_IOCTL_PANFROST_GET_PARAM 40

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13894>
 2021-11-22 13:12:20 +00:00
Alyssa Rosenzweig
a777e38cf9 panfrost: Collapse 0 parameters in drm-shim 
Makes the code a bit more readable, since this is a sensible default for
many parameters.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13894>
 2021-11-22 13:12:20 +00:00
Lionel Landwerlin
8657fa6b86 pps: allow drivers to report timestamps in their own time domain 
For this each driver must :

  - report its clock_id (if no particular clock just default to cpu
    boottime one)

  - be able to sample its clock (gpu_timestamp())

The PPSDataSource will then emit timestamp correlation events in the
trace ensuring perfetto is able to display GPU & CPU events
appropriately on its timeline.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
 2021-11-22 11:52:46 +00:00
Alyssa Rosenzweig
e346ca5b41 pan/bi: Add XML for LD_BUFFER 
Encoded like LOAD.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
69ddbc4341 pan/bi: Suppress uniform validation for LD_BUFFER 
Seems to be ok and used by the DDK...

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
36486f54e9 pan/bi: Confirm IDP unit on Valhall 
Based on Anandtech which gives 8-bit dot product throughput on Valhall
under FMA and not consistent with SFU.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
b8ba909ca6 pan/bi: Forbid unaligned staging registers on Valhall 
Would've saved me some debugging with the computerator. I keep
forgetting about this nuance. Enforce it in the assembler.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
df807cb839 pan/bi: Add XML for assembling Valhall image stores 
Not complete yet but let's get some tests in early. Document the new
instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
58b65a340c pan/bi: Add Valhall's special FMA_RSCALE instructions 
Like Bifrost, but exposed as separate physical instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
aee819d54c pan/bi: Add sqrt form of Valhall FREXPM 
Like Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
137053c4f4 pan/bi: Add full form of Valhall MUX instruction 
Like Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
855ab23d9a pan/bi: Annotate Valhall instructions with units 
Based on analyzing the cycle counts reported by the Mali offline
compiler.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
4e83584092 pan/mdg: Remove duplicate compiler option 
Noted by clang.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
 2021-11-12 16:30:02 +00:00
Alyssa Rosenzweig
a4d3a29647 pan/bi: Enable dual texture fusing pass 
Everything is in place for it now -- ship it! Our Bifrost cycle model is
coarse, so take the shader-db results with a massive spoonful of salt:

total instructions in shared programs: 107504 -> 107252 (-0.23%)
instructions in affected programs: 39692 -> 39440 (-0.63%)
helped: 191
HURT: 1
helped stats (abs) min: 1.0 max: 20.0 x̄: 1.32 x̃: 1
helped stats (rel) min: 0.11% max: 9.52% x̄: 1.21% x̃: 0.98%
HURT stats (abs)   min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 2.04% max: 2.04% x̄: 2.04% x̃: 2.04%
95% mean confidence interval for instructions value: -1.60 -1.02
95% mean confidence interval for instructions %-change: -1.37% -1.01%
Instructions are helped.

total tuples in shared programs: 89864 -> 89664 (-0.22%)
tuples in affected programs: 27787 -> 27587 (-0.72%)
helped: 146
HURT: 6
helped stats (abs) min: 1.0 max: 17.0 x̄: 1.54 x̃: 1
helped stats (rel) min: 0.14% max: 15.38% x̄: 1.83% x̃: 1.25%
HURT stats (abs)   min: 1.0 max: 11.0 x̄: 4.17 x̃: 2
HURT stats (rel)   min: 0.54% max: 3.55% x̄: 1.29% x̃: 0.87%
95% mean confidence interval for tuples value: -1.64 -0.99
95% mean confidence interval for tuples %-change: -2.06% -1.36%
Tuples are helped.

total clauses in shared programs: 18253 -> 18044 (-1.15%)
clauses in affected programs: 5127 -> 4918 (-4.08%)
helped: 164
HURT: 1
helped stats (abs) min: 1.0 max: 19.0 x̄: 1.28 x̃: 1
helped stats (rel) min: 0.78% max: 28.57% x̄: 6.73% x̃: 5.88%
HURT stats (abs)   min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 2.94% max: 2.94% x̄: 2.94% x̃: 2.94%
95% mean confidence interval for clauses value: -1.50 -1.04
95% mean confidence interval for clauses %-change: -7.42% -5.91%
Clauses are helped.

total cycles in shared programs: 8118.54 -> 8103.88 (-0.18%)
cycles in affected programs: 414.96 -> 400.29 (-3.53%)
helped: 43
HURT: 27
helped stats (abs) min: 0.041665999999999315 max: 4.375 x̄: 0.41 x̃: 0
helped stats (rel) min: 0.24% max: 50.00% x̄: 11.49% x̃: 5.26%
HURT stats (abs)   min: 0.041665999999999315 max: 1.1666639999999973 x̄:
0.10 x̃: 0
HURT stats (rel)   min: 0.43% max: 4.71% x̄: 1.42% x̃: 1.28%
95% mean confidence interval for cycles value: -0.35 -0.07
95% mean confidence interval for cycles %-change: -9.50% -3.53%
Cycles are helped.

total arith in shared programs: 3375.67 -> 3376.42 (0.02%)
arith in affected programs: 345.29 -> 346.04 (0.22%)
helped: 24
HURT: 32
helped stats (abs) min: 0.041665999999999315 max: 0.5833329999999997 x̄:
0.09 x̃: 0
helped stats (rel) min: 0.24% max: 14.29% x̄: 2.82% x̃: 1.50%
HURT stats (abs)   min: 0.041665999999999315 max: 1.1666639999999973 x̄:
0.09 x̃: 0
HURT stats (rel)   min: 0.43% max: 4.71% x̄: 1.42% x̃: 1.28%
95% mean confidence interval for arith value: -0.04 0.07
95% mean confidence interval for arith %-change: -1.19% 0.39%
Inconclusive result (value mean confidence interval includes 0).

total texture in shared programs: 1275 -> 1157 (-9.25%)
texture in affected programs: 725.50 -> 607.50 (-16.26%)
helped: 192
HURT: 0
helped stats (abs) min: 0.5 max: 10.0 x̄: 0.61 x̃: 0
helped stats (rel) min: 2.86% max: 50.00% x̄: 25.20% x̃: 25.00%
95% mean confidence interval for texture value: -0.72 -0.51
95% mean confidence interval for texture %-change: -27.12% -23.27%
Texture are helped.

total vary in shared programs: 537.88 -> 536.12 (-0.33%)
vary in affected programs: 2.75 -> 1 (-63.64%)
helped: 1
HURT: 0

total quadwords in shared programs: 79762 -> 79681 (-0.10%)
quadwords in affected programs: 10261 -> 10180 (-0.79%)
helped: 59
HURT: 18
helped stats (abs) min: 1.0 max: 14.0 x̄: 1.88 x̃: 1
helped stats (rel) min: 0.38% max: 8.20% x̄: 1.95% x̃: 1.43%
HURT stats (abs)   min: 1.0 max: 4.0 x̄: 1.67 x̃: 1
HURT stats (rel)   min: 0.46% max: 8.89% x̄: 2.22% x̃: 1.21%
95% mean confidence interval for quadwords value: -1.57 -0.53
95% mean confidence interval for quadwords %-change: -1.59% -0.37%
Quadwords are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
 2021-11-12 16:30:02 +00:00
Alyssa Rosenzweig
0c215813f7 pan/bi: Test dual texture fusing 
These patterns are quite tricky, so let's make sure we're testing
adequately.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
 2021-11-12 16:30:02 +00:00
Alyssa Rosenzweig
9146bafbb4 pan/bi: Add dual texture fusing pass 
Bifrost supports a special "dual texture" instruction, sampling from two
textures at once at the same coordinate. Each subinstruction is highly
restricted (a subset of TEXS_2D); together, they are represented by TEXC
with a special dual texture operation descriptor. Add an optimization
pass to fuse these instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
 2021-11-12 16:30:02 +00:00
Alyssa Rosenzweig
e6c6a1afb4 pan/bi: Fix up dual texturing registers 
This must be done after RA. How delightful. Use the GenXML strategy to
just OR the birds.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
 2021-11-12 16:30:02 +00:00
Alyssa Rosenzweig
ce8d2b96c1 pan/bi: Add bi_dual_tex_as_u32 helper 
Type safe cast, making dual texture descriptors easier to manipulate.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
 2021-11-12 16:30:02 +00:00
Alyssa Rosenzweig
9b2a383af8 pan/bi: Support dual texture scheduling 
Teach the scheduler about dual texturing to avoid an artifical "must not
last" constraint causing suboptimal scheduling like

clause_1:
ds(0) nbb tex ncph dwb(0)
{
    *NOP t0
    +TEXC.skip t1, r0, r1, 0xf1e00144, @r4
    *NOP t0
    +NOP t1
}

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
 2021-11-12 16:30:02 +00:00
Alyssa Rosenzweig
98c1b3e7e1 pan/bi: Use BIFROST_TEXTURE_OPERATION_SINGLE enum 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
 2021-11-12 16:30:02 +00:00
Alyssa Rosenzweig
9245b39ccf pan/bi: Add bifrost_dual_texture_operation struct 
This is the other state of the texture operation descriptor. We must
pack it in the compiler when fusing dual texturing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
 2021-11-12 16:30:02 +00:00
Alyssa Rosenzweig
3612880ea3 pan/bi: Add bifrost_texture_operation_mode enum 
Differentiates single/dual texturing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
 2021-11-12 16:30:02 +00:00
Alyssa Rosenzweig
7dc90b68d9 pan/bi: Add second destination to TEXC 
Used to model dual texturing, which writes to separate sets of staging
registers.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
 2021-11-12 16:30:02 +00:00
Alyssa Rosenzweig
8e02731624 pan/bi: Add secondary staging count 
Useful for instructions with two independent sets of staging registers
(like dual source blending or dual texturing).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
 2021-11-12 16:30:02 +00:00
Alyssa Rosenzweig
238f6d80a7 pan/bi: Make bi_index padding explicit 
Avoids reliance on UB.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
 2021-11-12 16:30:02 +00:00