Commit graph

194585 commits

Author SHA1 Message Date
Valentine Burley
e4933d1d90 zink/ci: Document recent flakes on TGL
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36409>
2025-08-13 14:48:32 +00:00
Valentine Burley
4ba1128600 zink/ci: Add EGL coverage on lavapipe
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36409>
2025-08-13 14:48:32 +00:00
Valentine Burley
72af71a17a zink/ci: Run full zink-lavapipe job pre-merge
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36409>
2025-08-13 14:48:32 +00:00
Yonggang Luo
e54d5c9c13 virgl: Fixes differs in parameter lists
../src/gallium/drivers/virgl/virgl_context.c(1783): error C2220: the following warning is treated as an error
../src/gallium/drivers/virgl/virgl_context.c(1783): warning C4113: 'void (__cdecl *)(pipe_context *,pipe_fence_handle **,pipe_flush_flags)' differs in parameter lists from 'void (__cdecl *)(pipe_context *,pipe_fence_handle **,unsigned int)'

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36726>
2025-08-13 14:22:19 +00:00
Yonggang Luo
671bd2d7da virgl: Fixes warning: cast to smaller integer type 'unsigned long' from 'void *' [-Wvoid-pointer-to-int-cast]
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36726>
2025-08-13 14:22:19 +00:00
Corentin Noël
f78a52fd0a tgsi: Drop TGSI_SEMANTIC_TESS_DEFAULT_OUTER/INNER_LEVEL
Nothing is emitting this anymore and it is not used by virglrenderer too.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36758>
2025-08-13 13:55:01 +00:00
Yonggang Luo
e14a9e7fe4 util: Remove dbghelp.h that already comes with winsdk and mingw for fix warning with mingw
The warning is:
../../src/util/dbghelp.h:900:10: warning: the current #pragma pack alignment value is modified in the included file [-Wpragma-pack]
  900 | #include <pshpack4.h>

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36708>
2025-08-13 13:18:52 +00:00
Roland Scheidegger
67b90113a6 llvmpipe: Fix wrong GS invocation count when using instanced GS
Some checks are pending
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Each invocation obviously counts toward the total GS invocation count.

Reviewed-by: Brian Paul <brian.paul@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36686>
2025-08-13 12:52:42 +00:00
Lionel Landwerlin
c871a62a75 brw: move URB channel mask shifting to the lowering pass
For example Xe2 uses the LSC and doesn´t need the shifting, so let's
just apply it where it's needed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36757>
2025-08-13 12:01:49 +00:00
Lionel Landwerlin
99cf8273f6 anv: stop using descriptor layouts for descriptor buffers push sizes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36757>
2025-08-13 12:01:49 +00:00
Lionel Landwerlin
68838d7001 brw: reorder reloc enums to leave embedded samplers at the end
So that the driver can allocate an array of relocations using
BRW_SHADER_RELOC_EMBEDDED_SAMPLER_HANDLE + number_of_embedded_samplers

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36757>
2025-08-13 12:01:49 +00:00
Lionel Landwerlin
69a04151db vulkan/runtime: add ray tracing pipeline support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36757>
2025-08-13 12:01:49 +00:00
Lionel Landwerlin
daac500e98 vulkan/runtime: add a few more shader properties
Ray tracing pipelines can contain unlimited number of shaders unlike
compute/graphics ones. Having the driver finding the maximum
scratch/ray-query/stack usage can be time consumming when this can be
stored on the pipeline and the runtime tell the driver at bind time.

These fields are unused for other shaders and so drivers can ignore
them.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36757>
2025-08-13 12:01:49 +00:00
Yonggang Luo
c321f61c21 microsoft/compiler: Fixes dxcapi.h compiling warning with mingw64-clang
The warning is:
dxcapi.h:694:1: warning: adding 'int' to a string does not append to the string [-Wstring-plus-int]
  694 | CROSS_PLATFORM_UUIDOF(IDxcVersionInfo2, "fb6904c4-42f0-4b62-9c46-983af7da7c83")
      | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../src/microsoft/compiler/dxcapi.h:114:59: note: expanded from macro 'CROSS_PLATFORM_UUIDOF'
  114 |        byte_from_hexstr(spec + 32), byte_from_hexstr(spec + 34))

Note: spec is a string literal: "fb6904c4-42f0-4b62-9c46-983af7da7c83"

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36707>
2025-08-13 11:32:27 +00:00
Caleb Callaway
20171f23d6 spirv: Fix RT raygen hit attribute validation error
Some checks are pending
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Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13677
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36729>
2025-08-13 10:20:35 +00:00
Job Noorman
6d779e900c ir3: allow shared srcs for ldc
This works just fine and opens up a lot more opportunities for early
preamble. Note that I haven't seen actual cases where the index is large
enough to need a register but verified in computerator that it works.

Totals:
MaxWaves: 2377396 -> 2377428 (+0.00%); split: +0.00%, -0.00%
Instrs: 48194946 -> 48173991 (-0.04%); split: -0.10%, +0.06%
CodeSize: 101878832 -> 101892290 (+0.01%); split: -0.06%, +0.07%
NOPs: 8383282 -> 8362061 (-0.25%); split: -0.46%, +0.20%
MOVs: 1468620 -> 1464570 (-0.28%); split: -1.14%, +0.86%
COVs: 823514 -> 823506 (-0.00%); split: -0.00%, +0.00%
Full: 1716474 -> 1714338 (-0.12%); split: -0.13%, +0.01%
(ss): 1112861 -> 1117802 (+0.44%); split: -0.52%, +0.96%
(sy): 552143 -> 553148 (+0.18%); split: -0.31%, +0.49%
(ss)-stall: 4011510 -> 4018364 (+0.17%); split: -0.26%, +0.43%
(sy)-stall: 16736200 -> 16766871 (+0.18%); split: -0.39%, +0.57%
STPs: 18895 -> 18887 (-0.04%)
LDPs: 23853 -> 23845 (-0.03%)
Preamble Instrs: 11502184 -> 11461058 (-0.36%); split: -0.48%, +0.12%
Early Preamble: 121333 -> 125474 (+3.41%)
Last helper: 11683394 -> 11675574 (-0.07%); split: -0.14%, +0.07%
Subgroup size: 12951168 -> 12952320 (+0.01%)
Cat0: 9238171 -> 9217761 (-0.22%); split: -0.42%, +0.20%
Cat1: 2352968 -> 2348920 (-0.17%); split: -0.71%, +0.54%
Cat2: 17464877 -> 17468941 (+0.02%); split: -0.00%, +0.03%
Cat6: 515664 -> 515648 (-0.00%)
Cat7: 1636736 -> 1636191 (-0.03%); split: -0.33%, +0.29%

Totals from 12861 (7.81% of 164705) affected shaders:
MaxWaves: 141814 -> 141846 (+0.02%); split: +0.07%, -0.05%
Instrs: 12731084 -> 12710129 (-0.16%); split: -0.39%, +0.22%
CodeSize: 24749138 -> 24762596 (+0.05%); split: -0.23%, +0.29%
NOPs: 2744093 -> 2722872 (-0.77%); split: -1.40%, +0.62%
MOVs: 492373 -> 488323 (-0.82%); split: -3.39%, +2.57%
COVs: 170074 -> 170066 (-0.00%); split: -0.01%, +0.00%
Full: 224044 -> 221908 (-0.95%); split: -1.00%, +0.05%
(ss): 325836 -> 330777 (+1.52%); split: -1.76%, +3.28%
(sy): 143661 -> 144666 (+0.70%); split: -1.20%, +1.89%
(ss)-stall: 1397335 -> 1404189 (+0.49%); split: -0.75%, +1.24%
(sy)-stall: 4286193 -> 4316864 (+0.72%); split: -1.52%, +2.24%
STPs: 1628 -> 1620 (-0.49%)
LDPs: 2183 -> 2175 (-0.37%)
Preamble Instrs: 2486870 -> 2445744 (-1.65%); split: -2.23%, +0.57%
Early Preamble: 170 -> 4311 (+2435.88%)
Last helper: 3053311 -> 3045491 (-0.26%); split: -0.52%, +0.26%
Subgroup size: 991296 -> 992448 (+0.12%)
Cat0: 3031604 -> 3011194 (-0.67%); split: -1.29%, +0.61%
Cat1: 667377 -> 663329 (-0.61%); split: -2.50%, +1.90%
Cat2: 4485219 -> 4489283 (+0.09%); split: -0.01%, +0.10%
Cat6: 87365 -> 87349 (-0.02%)
Cat7: 731126 -> 730581 (-0.07%); split: -0.73%, +0.65%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36674>
2025-08-13 09:59:14 +00:00
Seán de Búrca
c579b8eff6 rusticl: adjust naming and assert usage for clarity
v2: make naming consistent across functions, incorporate earlier naming
changes

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
2025-08-13 09:37:45 +00:00
Seán de Búrca
808484041c rusticl: execute program builds as jobs on a worker thread
v2: rework to use Rust closure for worker job function
v3: split preparatory restructuring into separate commit
v4: parallelize link and compile, adjust thread/job count
v5: split out naming changes to later commit, move validation to api/

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
2025-08-13 09:37:45 +00:00
Seán de Búrca
56cc1b1c96 rusticl: restructure program build to prepare for parallelization
v2: include restructuring of link and compile, break out more functions
v3: split out naming changes to later commit

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
2025-08-13 09:37:45 +00:00
Seán de Búrca
833481b6ab rusticl: introduce intermediate header object
This lets us take ownership of the header object without worrying about
lifetimes, enabling parallelization.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
2025-08-13 09:37:44 +00:00
Seán de Búrca
e6fb1d5d32 rusticl: add abstraction for util_queue
v2: rework to use Rust closures for passed-in job function
v3: drop mutability requirement on queue for adding a job
v4: prevent external creation of fences, return from add_job_sync()
v5: add CPU count utility function based on util_get_cpu_caps()
v6: use &CStr for queue name for convenience
v7: make fence Send + Sync and don't require mutability for waiting

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
2025-08-13 09:37:44 +00:00
Seán de Búrca
1ac5b99301 rusticl: consolidate linking code
v2: split out functional change to prior commit

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
2025-08-13 09:37:44 +00:00
Seán de Búrca
a6f96a18d8 rusticl: release borrow on device build before linking
This allows for a later refactor to share linking code between
clBuildProgram and clLinkProgram in which the device build is borrowed
mutably.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
2025-08-13 09:37:43 +00:00
Seán de Búrca
8f71f1527a rusticl: clarify naming of program-related structs and fields
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
2025-08-13 09:37:43 +00:00
Seán de Búrca
cc05dc584e rusticl: disentangle ProgramBuild state from kernel compilation
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
2025-08-13 09:37:42 +00:00
Seán de Búrca
5cb328d002 rusticl: move debug logging to the end of the build step
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
2025-08-13 09:37:42 +00:00
Karol Herbst
beadc1f93a anv/i915: print bo->map when dumping exec buffers bos
Some checks are pending
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This makes it easier to verify if the host allocation a user-ptr bo is
assigned to still exists. The kernel rejects command submissions with
user-ptr bos pointing to non-mapped host memory, so this makes it easier
to debug those.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36701>
2025-08-13 08:30:43 +00:00
Karol Herbst
e31d5bc5a9 zink: set zink_bo is_user_ptr on creation
We need to release user_ptr resources earlier, so we don't keep stale
references around, but for that to happen we also need to know which
resource is a user_ptr one in the first place.

Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36701>
2025-08-13 08:30:43 +00:00
Karol Herbst
8d8f5558eb anv: do not map from_host_ptr bos in image_bind_address
Rusticl running on zink might end up creating an 1D image from a host_ptr
and zink might bind it with VK_IMAGE_USAGE_HOST_TRANSFER_BIT_EXT.

That ended up hitting an assert inside anv_device_map_bo.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36701>
2025-08-13 08:30:43 +00:00
Lionel Landwerlin
a973fb1bb0 anv: fix missing meson dep
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13627
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36737>
2025-08-13 08:10:39 +00:00
Job Noorman
9b418671cf ir3: don't add array stores to block keeps
Array accesses (including stores) are fully converted to SSA. This means
ir3_dce can handle them correctly and we don't have to forcefully keep
them around.

Totals:
MaxWaves: 2381954 -> 2382720 (+0.03%)
Instrs: 49073677 -> 49056449 (-0.04%)
CodeSize: 102537524 -> 102485082 (-0.05%); split: -0.05%, +0.00%
NOPs: 8396340 -> 8405825 (+0.11%)
MOVs: 1450777 -> 1433266 (-1.21%)
COVs: 825142 -> 822678 (-0.30%)
Full: 1714304 -> 1712751 (-0.09%)
(ss): 1126433 -> 1126611 (+0.02%); split: -0.00%, +0.02%
(sy): 554174 -> 554194 (+0.00%); split: -0.00%, +0.00%
(ss)-stall: 4013834 -> 4014314 (+0.01%)
(sy)-stall: 16713036 -> 16713790 (+0.00%); split: -0.00%, +0.01%
LDPs: 23957 -> 23701 (-1.07%)
Preamble Instrs: 11106162 -> 11105987 (-0.00%)
Cat0: 9252109 -> 9261512 (+0.10%)
Cat1: 2337941 -> 2317966 (-0.85%)
Cat2: 18452467 -> 18448379 (-0.02%)
Cat3: 14099754 -> 14097262 (-0.02%)
Cat4: 1362443 -> 1362435 (-0.00%)
Cat6: 515831 -> 515767 (-0.01%)
Cat7: 1636810 -> 1636806 (-0.00%)

Totals from 417 (0.25% of 164705) affected shaders:
MaxWaves: 5552 -> 6318 (+13.80%)
Instrs: 160717 -> 143489 (-10.72%)
CodeSize: 367044 -> 314602 (-14.29%); split: -14.30%, +0.01%
NOPs: 29576 -> 39061 (+32.07%)
MOVs: 25110 -> 7599 (-69.74%)
COVs: 5276 -> 2812 (-46.70%)
Full: 6879 -> 5326 (-22.58%)
(ss): 3484 -> 3662 (+5.11%); split: -0.32%, +5.42%
(sy): 2486 -> 2506 (+0.80%); split: -0.12%, +0.93%
(ss)-stall: 8949 -> 9429 (+5.36%)
(sy)-stall: 124684 -> 125438 (+0.60%); split: -0.28%, +0.89%
LDPs: 256 -> 0 (-inf%)
Preamble Instrs: 60629 -> 60454 (-0.29%)
Cat0: 33230 -> 42633 (+28.30%)
Cat1: 30386 -> 10411 (-65.74%)
Cat2: 43140 -> 39052 (-9.48%)
Cat3: 26251 -> 23759 (-9.49%)
Cat4: 1148 -> 1140 (-0.70%)
Cat6: 102 -> 38 (-62.75%)
Cat7: 13332 -> 13328 (-0.03%)

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36720>
2025-08-13 07:05:12 +00:00
Lionel Landwerlin
9a6065852d anv: Do not consider task as prerasterization
What drivers state programming in the 3D pipeline is the mesh shader.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36734>
2025-08-13 06:24:44 +00:00
Lionel Landwerlin
46c16f854e brw: compute consistent clip/cull distance masks with VUE
We can optimize the VUE layout in cases where all shaders are compiled
together and some outputs are unused. So we need to have consistent
clip/cull_distance_mask with the VUE.

Previously we could have a VUE without ClipDistance present in the
header and yet have a non zero clip_distance_mask. This would trip the
HW into taking into account a VUE field that doesn't exist.

Here we set the clip/cull_distance_mask to 0 if the associated output
is not written by the shader. The written outputs are always
consistent with what's in the VUE.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2d396f6085 ("intel: prepare VUE layout for more than 2 layouts")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13685
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36734>
2025-08-13 06:24:44 +00:00
Sagar Ghuge
cac3b4f404 anv: Mask off excessive invocations
Some checks are pending
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macOS-CI / macOS-CI (xlib) (push) Waiting to run
For unaligned invocations, don't launch two COMPUTE_WALKER, instead we
can mask off excessive invocations in the shader itself at nir level and
launch one additional workgroup.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36245>
2025-08-12 23:17:02 +00:00
Sagar Ghuge
7b634ebb63 vulkan/runtime: Add VK_SHADER_CREATE_UNALIGNED_DISPATCH_BIT_MESA flag
Drivers that doesn't support direct unaligned dispatches, they can use
the shader creation flag to lower unaligned dispatches.

Suggested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36245>
2025-08-12 23:17:02 +00:00
Sagar Ghuge
349de5b0be anv: Use vk_get_bvh_build_pipeline_spv helper
Took inspiration from RADV driver changes. This allow us to get rid of
our local helper get_pipeline_spv().

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36245>
2025-08-12 23:17:02 +00:00
Karol Herbst
20b2944274 rusticl: silence new warnings from rustc versions above our rustc target
Some checks are pending
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Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36747>
2025-08-12 22:37:52 +00:00
Karol Herbst
ea69a01378 rusticl: silence warnings in generated sources
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36747>
2025-08-12 22:37:52 +00:00
David Rosca
09dd2bc388 rusticl/ptr: Fix hidden lifetime warning
error: hiding a lifetime that's elided elsewhere is confusing
   --> ../src/gallium/frontends/rusticl/util/ptr.rs:166:18
    |
166 |     pub fn entry(&mut self, ptr: P) -> Entry<P, T> {
    |                  ^^^^^^^^^             ----------- the same lifetime is hidden here
    |                  |
    |                  the lifetime is elided here

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36747>
2025-08-12 22:37:52 +00:00
Faith Ekstrand
47ef0d2470 nvk: Allow kepler in nvk_is_conformant()
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Thanks to "Enable X platform" patches living way too long (Vulkan
conformance has a 30 day delay), there was a little rebase fail and we
turned on Kepler and then accidentally turned it back off.

Fixes: f4b01bbfe7 ("nvk: Add an nvk_is_conformant() helper")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36745>
2025-08-12 19:50:21 +00:00
Robert Mader
3f995bf817 anv: Enable G8_B8_R8_3PLANE_422 and G8_B8_R8_3PLANE_444 formats
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They are well supported and useful for efficient playback of software
decoded videos - e.g. when allocating buffers with udmabuf or dma heaps
and then importing them into Vulkan.

Signed-off-by: Robert Mader <robert.mader@posteo.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35273>
2025-08-12 19:16:29 +00:00
Sagar Ghuge
ba1ddb6b62 vulkan/radix_sort: Fix subgroup invocation id
When we have single subgroup within a workgroup, I guess we want to
index invocation within the subgroup, we don't want the ID of subgroup
within local workgroup, since it will be always 0.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36733>
2025-08-12 18:39:20 +00:00
Yiwei Zhang
1abe0d38d1 vulkan/util: update common properties code gen to use platform guard
Similar to the prior feature code gen update. This one here also absorbs
the Android private ANB struct.

Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36702>
2025-08-12 18:12:50 +00:00
Yiwei Zhang
9999cd3967 vulkan/util: no need to hide ANB property itself behind Android
Property members are never going to use platform specific struct.
Getting rid of the guard around sharedImage propperty simplifies driver
side setting the prop.

Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36702>
2025-08-12 18:12:50 +00:00
Yiwei Zhang
567cff487c vulkan/util: add missing vulkan header
Unlike features, property members do need Vulkan header. Currently it
relies on the fact that vk_physical_device.h has included some other
headers that include vulkan.h before this.

Cc: mesa-stable
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36702>
2025-08-12 18:12:50 +00:00
Lucas Fryzek
23d7c3fbd5 vulkan/util: update pd feature codegen to use platform guards
If a given physical device feature needs a platform specific define
guard, generate the appropriate one instead of just ignoring it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36702>
2025-08-12 18:12:50 +00:00
Aaron Ruby
796e11008d vulkan/wsi: No commandPool allocation required for WSI_SWAPCHAIN_NO_BLIT
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commandPools/cmdBuffers are only required for swapchain configurations
that use a blit-queue. They do not need to be allocated at all in the
"no blit" configuration.

There are some validUsage issues with the commandPool allocation, namely
that the WSI impl assumes that the logical device was created with all
queueFamilies made available to it. This is an invalid assumption that
can result in: VUID-vkCreateCommandPool-queueFamilyIndex-01937 invalid
usage on the eventual call to the driver. Note: invalid usage by WSI
wouldn't normally be detectable without virtualization.

This change reduces the scope of that invalid usage.

Reviewed-by: Gurchetan Singh <gurchetansingh@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36361>
2025-08-12 11:44:24 -04:00
Gert Wollny
8c65da0c9d r600/sfn: cleanup GS shader emission
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Now that we lower all load_per_vertex_input to
r600_load_per_vertex_input we can remove some dead code
and also change the intrinsic to use only one source value.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
2025-08-12 14:30:17 +00:00
Gert Wollny
eccd178f0b r600/sfn: Lower all GS indirect input loads after lowering IO
Extend the lowering of indirect GS array inputs to include
all indirect access. This replaces
   r600_gs_load_deref_io_to_indirect_per_vertex_input
which was restricted to vec4 POS inputs. The
new lowering pass works in all vayings and all types, so we
can also drop the call to nir_lower_indirect_derefs.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
2025-08-12 14:30:16 +00:00
Gert Wollny
356bc41797 r600/sfn: resolve constant indices into local arrays better
When the code is first generated constants are loaded to registers, so to
avoid indirect array register access that can be resolved as a direct direct
access we have to check whether the address register is loaded
with a constant value.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
2025-08-12 14:30:15 +00:00