Commit graph

316 commits

Author SHA1 Message Date
Tapani Pälli
10cdfce14e intel/common: disable batch decoder on Android platform
when building with Meson. It requires libexpat that is not available
on Android and we want to avoid it.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9848>
2021-03-27 19:26:22 +02:00
Marcin Ślusarz
08f8677b29 intel/batch_decoder: assert on invalid sampler pointer
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
2021-03-22 08:36:55 +00:00
Marcin Ślusarz
56cd91bc7c intel/batch_decoder: fix decoding of sampler states
There's only 1 sampler state behind
3DSTATE_SAMPLER_STATE_POINTERS[_VS|_HS|_DS|_GS|_PS] and
3DSTATE_SAMPLER_STATE_POINTERS.[PointertoVSSamplerState|PointertoPSSamplerState|PointertoGSSamplerState].

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
2021-03-22 08:36:55 +00:00
Marcin Ślusarz
cd0f9cdb6e intel/batch_decoder: drop bogus check
state_addr == bo.addr, bo.size==0 is handled by another check

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
2021-03-22 08:36:55 +00:00
Marcin Ślusarz
bb8ee5f52d intel/batch_decoder: catch invalid sampler state pointer
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
2021-03-22 08:36:55 +00:00
Jason Ekstrand
731ea06758 intel/tools: Handle BINDING_TABLE_POOL_ALLOC in batch decoding
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
2021-03-20 12:46:50 -05:00
Jason Ekstrand
05e133a84a intel/tools: Handle GT_MODE in the batch decoder
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
2021-03-20 12:46:50 -05:00
Jason Ekstrand
b2421f7b44 intel/tools: Handle milti-LRI in the batch decoder
Context batches tend to have a lot of multi-LRI and, if we want to be
able to parse those registers nicely, we really handle it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
2021-03-20 12:33:18 -05:00
Lionel Landwerlin
33bc2977e5 intel/mi_builder: use device info to use the right CS prefetch size
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9679>
2021-03-18 20:08:45 +00:00
Anuj Phogat
1d0295ea2c intel: Simplify version checks involving haswell
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9608>
2021-03-16 16:40:12 +00:00
Anuj Phogat
97d6ceaf04 intel: Remove GEN_IS_HASWELL macro
Use GEN_VERSIONx10 == 75 check in place of GEN_IS_HASWELL macro.
GEN_GEN and GEN_VERSIONx10 macros provide a consistent way to do platform
version checks. We can avoid platform specific macros.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9608>
2021-03-16 16:40:12 +00:00
Anuj Phogat
96e251bde7 intel: Rename "GEN_" prefix used in common code to "INTEL_"
This patch renames all macros with "GEN_" prefix defined in
common code.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9413>
2021-03-10 22:23:51 +00:00
Anuj Phogat
65d7f52098 intel: Fix broken alignment due to gen_ prefix renaming
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9413>
2021-03-10 22:23:51 +00:00
Anuj Phogat
692472a376 intel: Rename "gen_" prefix used in common code to "intel_"
This patch renames functions, structures, enums etc. with "gen_"
prefix defined in common code.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9413>
2021-03-10 22:23:51 +00:00
Anuj Phogat
733b0ee8cb intel: Rename files with gen_ prefix in common code to intel_
Changes in this patch include:
- Rename all files in src/intel/common path
- Update the filenames used in source and build files

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9413>
2021-03-10 22:23:51 +00:00
Fan Yugang
6905122999 intel/tools: Show unknown instructions in decoded state.
Signed-off-by: Fan Yugang <yugang.fan@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9455>
2021-03-09 09:36:08 +00:00
Jason Ekstrand
25020c125a intel/mi_builder: Fix a couple of #ifs
All this does is remove a field on Gen7 and stop asserting on it.  No
actual functional change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9467>
2021-03-08 16:14:13 -06:00
Jason Ekstrand
62c64e7b9d intel/mi_builder: Fix some indentation
This got lost in the rebase on top of the s/gen_mi_/mi_/ change

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9467>
2021-03-08 16:13:37 -06:00
Jason Ekstrand
98a5b9b454 intel/mi_builder: Add control-flow support
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
2021-03-08 10:47:19 -06:00
Jason Ekstrand
8525ebe6e3 intel/mi_builder: Return an address from __gen_get_batch_address
While we're here, add __gen_get_batch_address declarations to more files
because we're about to start requiring it on all GFX 12.5+.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
2021-03-08 10:47:19 -06:00
Jason Ekstrand
322fba216b intel/mi_builder: Use softpin for tests on gen8+
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
2021-03-08 10:47:19 -06:00
Jason Ekstrand
c23f7f1154 intel/batch_decoder: Don't follow predicated MI_BATCH_BUFFER_START
The stuff after these may be executed so we want to decode it too.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
2021-03-08 10:47:19 -06:00
Jason Ekstrand
c7c524337a intel/mi_builder: Add load/store_offest on GFX 12.5+
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
2021-03-08 10:47:18 -06:00
Jason Ekstrand
6323a8522b intel/mi_builder: Support inverted values in mi_store
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
2021-03-08 10:45:45 -06:00
Sagar Ghuge
04d0d4e849 intel/mi_builder: Added support for command streamer shift operations
Add logical shift left and right operations support to mi_builder.

v1:
- Add GEN_GEN > 12 check (Jordan Justen)
- Add gen_mi_has_shift function (Jordan Justen)
- Fix commit title (Jordan Justen)

v2 (Jason Ekstrand):
- Add _imm versions of all of them
- Better handle corner-cases in _imm helpers
- Handle the power-of-two limitation for _imm versions
- Add tests

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
2021-03-08 10:45:42 -06:00
Jason Ekstrand
62b9e30cc7 intel/mi_builder: Add ieq/ine helpers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
2021-03-08 10:45:24 -06:00
Jason Ekstrand
2c02740a8c intel/mi_builder: Use AddCSMMIOStartOffset for LRI
In 06cf838cbd we started using the AddCSMMIOStartOffset feature
on Gen11+ but we missed one place.

Fixes: 06cf838cbd "intel/mi_builder: Support gen11 command-streamer..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
2021-03-08 09:54:45 -06:00
Jason Ekstrand
1e53e0d2c7 intel/mi_builder: Drop the gen_ prefix
mi_ is already a unique prefix in Mesa so the gen_ isn't really gaining
us anything except extra characters.  It's possible that MI_ may
conflict a tiny bit with GenXML but it doesn't seem to be a problem
today and we can deal with that in the future if it's ever an issue.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9393>
2021-03-04 15:14:27 +00:00
Jason Ekstrand
6d522538b6 intel: Rename gen_mi_builder.h to mi_builder.h
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9393>
2021-03-04 15:14:27 +00:00
Mark Janes
f54a65c69b intel: check setuid before writing output file in INTEL_MEASURE
Without this check, the INTEL_MEASURE environment variable could be
misused to overwrite arbitrary files.

Fixes: 0f4143ec37 ("intel: Print GPU timing data based on INTEL_MEASURE")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9166>
2021-02-20 11:53:33 -08:00
Jason Ekstrand
7c8c14a988 intel/mi_builder: Add tests for gen_mi_z and gen_mi_nz
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9116>
2021-02-18 21:28:40 +00:00
Jason Ekstrand
9145d77707 intel/mi_builder: Rewrite unit tests in terms of constant folding
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9116>
2021-02-18 21:28:40 +00:00
Jason Ekstrand
efdbe53eda intel/mi_builder: Add constant folding
This also serves as pretty clear documentation of each helper's
semantics.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9116>
2021-02-18 21:28:40 +00:00
Jason Ekstrand
dbcbb321ad intel/mi_builder: Short-circuit shifts in more cases
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9116>
2021-02-18 21:28:40 +00:00
Jason Ekstrand
c64d7aa8e3 intel/mi_builder: Fix a misleading comment
This doesn't actually assume the top 32 bits of the source value are
zero.  Instead, it does (src >> shift) & UINT32_MAX regardless of what
the top bits of src are.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9116>
2021-02-18 21:28:40 +00:00
Jason Ekstrand
40df12d4ce intel/mi_builder: Delete a bogus comment
It actually returns ~0/0.  We're about to make things more self-
documenting so we can delete the comment instead of fixing it.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9116>
2021-02-18 21:28:40 +00:00
Jason Ekstrand
749ae5af93 intel/mi_builder: Create a context in the tests
This makes them work on the simulator

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9116>
2021-02-18 21:28:40 +00:00
Rohan Garg
628c10f14e intel/genxml: Free resource before exiting
Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8162>
2021-02-16 15:07:52 +01:00
Mark Janes
2edfb27913 intel: combine common gather routines in INTEL_MEASURE
Anv and iris had separate, similar routines to gather intel_measure
timestamps.  Timestamps are now managed within intel_measure, allowing
those routines to be consolidated.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7354>
2021-02-01 17:24:57 -08:00
Mark Janes
d6fc72e286 intel: support secondary command buffers in INTEL_MEASURE
When a secondary command buffer is encountered, insert an event that
links to the new batch.

This commit leaves intel_measure timestamp buffer objects mmapped,
which is more efficient than mapping/unmapping several times.  With
the BOs mapped at all times, timestamp buffers can be managed directly
by intel_measure, where it will iterate over timestamps of linked
secondary buffers.

With timestamp buffers managed by intel_measure, a more efficient and
accurate check for render completion can be moved into intel_measure
from anv/iris.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7354>
2021-02-01 17:24:57 -08:00
Mark Janes
9eacbfaf7b intel: stop tracking submission state in INTEL_MEASURE
With secondary command buffers, it is inconvenient to track whether a
batch has been submitted and needs to be gathered.  Instead, always
check for completed snapshots before destroying a command buffer.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7354>
2021-02-01 17:24:57 -08:00
Mark Janes
0f4143ec37 intel: Print GPU timing data based on INTEL_MEASURE
This infrastructure collects GPU timestamps over common intervals, and
generates a CSV report to show how long rendering took.  The overhead
of collection is limited to the flushing that is required at the
interval boundaries for accurate timestamps.

By default, timing data is sent to stderr.  To direct output to a
file:
 INTEL_MEASURE=file=/tmp/measure.csv {workload}

To begin capturing timestamps at a particular frame:
 INTEL_MEASURE=file=/tmp/measure.csv,start=15 {workload}

To capture only 23 frames:
 INTEL_MEASURE=count=23 {workload}

To capture frames 15-37, stopping before frame 38:
 INTEL_MEASURE=start=15,count=23 {workload}

Designate an asynchronous control file with:
 INTEL_MEASURE=control=path/to/control.fifo {workload}

As the workload runs, enable capture for 5 frames with:

 $ echo 5 > path/to/control.fifo

Enable unbounded capture:

 $ echo -1 > path/to/control.fifo

and disable with:

 $ echo 0 > path/to/control.fifo

Select the boundaries of each snapshot with:
 INTEL_MEASURE=draw  : DEFAULT - Collects timings for every render
 INTEL_MEASURE=rt    : Collects timings when the render target changes
 INTEL_MEASURE=batch : Collects timings when batches are submitted
 INTEL_MEASURE=frame : Collects timings at frame boundaries

With INTEL_MEASURE=interval=5, the duration of 5 events will be
combined into a single record in the output.  When possible, a single
start and end event will be submitted to the GPU to minimize
stalling.  Combined events will not span batches, except in
the case of INTEL_MEASURE=frame.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7354>
2021-02-01 17:24:57 -08:00
Lionel Landwerlin
43acc10bd0 intel/common: store sample position in plain arrays
Allows to extract the values in different ways than just the genxml
format.

v2 (Jason Ekstrand):
 - Add a struct gen_sample_location so that we can re-use the array
   macros from the earlier commit.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1887>
2021-01-27 23:25:27 +00:00
Eleni Maria Stea
cb082d8260 anv/state: Take explicit sample locations in emit helpers
This commit adds a "locations" parameter to emit_multisample and
emit_sample_pattern which, if provided, will override the default
sample locations.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1887>
2021-01-27 23:25:27 +00:00
Kenneth Graunke
a710145b5b intel: Produce a "constrained" output from gen_get_urb_config()
When calculating a URB configuration, we start with a notion of how
much space each stage /wants/ (to achieve the maximum amount of
concurrency), but sometimes fall back to giving it less than that,
because we don't have enough space.  (Typically, this happens when
the per-stage size is large, or there are many stages, or both.)

We now output a "constrained" boolean which is true if we weren't
able to satisfy all the "wants" due to a lack of space.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8721>
2021-01-27 18:30:54 +00:00
Lionel Landwerlin
d8154c4006 intel/mi_builder: fix self modifying batches
So far we only write a maximum of 4 dwords further into the batch and
it seems just going over the CS prefetch was enough.

Turns out writing more dwords can delay the writes and we start
prefetching stuff that hasn't landed in memory yet.

This fixes the issue by stalling the CS to ensure the writes have
landed before we go over the prefetch.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 796fccce63 ("intel/mi-builder: add framework for self modifying batches")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Lionel Landwerlin
359312ae01 intel/mi_builder: optimize 64bit immediate register loads & memory stores
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Jason Ekstrand
b7c1ad00fc intel/tools: Decode COMPUTE_WALKER
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:27 -08:00
Jordan Justen
231c27adaf intel/common: Build mi_builder_test for gen 12.5
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8424>
2021-01-11 13:05:49 -08:00
Michael Forney
434da21a7c meson: add missing dependency on generated git_sha1.h
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8121>
2020-12-17 00:03:22 +00:00