Samuel Pitoiset
d2e4435c20
radv: fix creating null devices if KHR_display is enabled
...
Found this while replaying pipelines with Fossilize, it worked
fine with vkpipeline-db.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3959 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3959 >
2020-02-26 10:28:46 +00:00
Samuel Pitoiset
4c03d20396
radv: make use of ac_gpu_info::max_wave64_per_simd
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899 >
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
9204ad70f2
radv/gfx10: adjust the number of VGPRs used to compute waves
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899 >
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
568f150409
radv/gfx10: adjust the LDS size used to compute waves
...
It's 128KB per CU in WGP.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899 >
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
ea91b15a31
radv/gfx10: adjust SGPRs/VGPRs related info
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899 >
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
a6df3ef6ec
radv/gfx10: adjust the number of simd per compute unit
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899 >
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
09d8726187
ac: add more ac_gpu_info related shader fields
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899 >
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
974c87e449
ac,radeonsi: add ac_gpu_info::lds_size_per_cu
...
Both RadeonSI and RADV use the WGP mode, so we can assume 128KB on
GFX10.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899 >
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
cd6ec2b1ab
radv: implement a dummy winsys for creating devices without AMDGPU
...
To allow developers to test the compiler backends without having
any AMD GPUs. To create a null device, set eg.
RADV_FORCE_FAMILY=polaris10 in your environment.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3872 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3872 >
2020-02-26 08:09:46 +01:00
Samuel Pitoiset
12a22da683
radv: add the trace BO to the BO list at submit time
...
Instead of adding it in every command buffer.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3891 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3891 >
2020-02-24 12:43:53 +01:00
Samuel Pitoiset
740cb3d193
radv: use RADEON_FLAG_ZERO_VRAM when creating the trace BO
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3888 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3888 >
2020-02-20 18:47:34 +01:00
Samuel Pitoiset
37650bf938
radv/winsys: add a new flag that requests zerovram allocations
...
This introduces RADON_FLAG_ZERO_VRAM.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3888 >
2020-02-20 18:47:29 +01:00
Rhys Perry
8291d728dc
aco: improve GFX9 1D ddx/ddy assertion
...
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2547
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3890 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3890 >
2020-02-20 15:41:26 +00:00
Rhys Perry
fe5c5507bd
aco: add some helpers for filling/testing register ranges
...
We do this a lot
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3768 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3768 >
2020-02-19 12:23:50 +00:00
Rhys Perry
43497e30e2
aco: add RegisterFile
...
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3768 >
2020-02-19 12:23:50 +00:00
Eric Anholt
13a276ed3b
radv: Squelch possibly-undefined warning
...
The same condition is used in the def as in the use, but gcc wasn't
figuring it out.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3867 >
2020-02-18 15:35:32 -08:00
Caio Marcelo de Oliveira Filho
28e94e0a94
radv: Advertise VK_KHR_shader_non_semantic_info
...
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3856 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3856 >
2020-02-18 09:57:17 -06:00
Samuel Pitoiset
c095b7d5bd
radv: add a comment about VK_AMD_mixed_attachment_samples on GFX6-GFX7
...
There is some CTS failures.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3808 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3808 >
2020-02-17 08:33:44 +01:00
Samuel Pitoiset
4159b24be7
radv: enable VK_NV_compute_shader_derivatives on GFX6-GFX7
...
All Crucible tests pass.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3808 >
2020-02-17 08:33:42 +01:00
Samuel Pitoiset
83dd0cace6
radv: enable VK_EXT_sampler_filter_minmax on GFX6
...
Works fine.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3808 >
2020-02-17 08:33:40 +01:00
Samuel Pitoiset
170c3a8b7b
radv: enable shaderStorageImageMultisample on GFX6-GFX7
...
It was disabled because untested, but CTS is happy with it.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3808 >
2020-02-17 08:32:26 +01:00
Samuel Pitoiset
886acbe1c5
radv: remove unnecessary RADV_DEBUG=nobatchchain option
...
It was used in the past but nowadays chained submissions work fine.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3791 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3791 >
2020-02-14 07:48:14 +01:00
Samuel Pitoiset
b9e0947a9e
radv: remove unused RADV_HASH_SHADER_IS_GEOM_COPY_SHADER
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789 >
2020-02-13 08:09:13 +00:00
Samuel Pitoiset
b2531370c9
radv: remove RADV_DEBUG=nosisched and RADV_PERFTEST=sisched
...
They are no longer useful.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789 >
2020-02-13 08:09:13 +00:00
Samuel Pitoiset
fa48e7edc2
radv: remove LLVM sicheduler enable for The Talos Principle
...
sisched is completely unmaintained, it used to give few more FPS
in the past but with ACO, it's now obsolete. It seems even faster
without sisched now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789 >
2020-02-13 08:09:13 +00:00
Samuel Pitoiset
556c940149
radv: implement VK_EXT_line_rasterization
...
Only Bresenham lines are supported. GFX9 is currently disabled
because there is some CTS failures for some weird reasons.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2982 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2982 >
2020-02-13 08:14:01 +01:00
Samuel Pitoiset
fbcf05382b
radv: fix line width range and granularity
...
The hardware supports wide lines and the granularity is way larger.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2982 >
2020-02-13 08:14:01 +01:00
Rhys Perry
483d4ec57c
aco: improve SCC handling in some SALU combines
...
Add some checks and remove some unnecessary checks.
Found by observation. No pipeline-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3599 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3599 >
2020-02-12 19:18:45 +00:00
Rhys Perry
d45e9451cf
aco: disable some instruction combining if it could change an exec operand
...
Found by observation. No pipeline-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3599 >
2020-02-12 19:18:40 +00:00
Arcady Goldmints-Orlov
e9f83185a2
Rename nir_lower_constant_initializers to nir_lower_variable_initalizers
...
This is naming is more clear as nir_variables can be initializes not
just with a nir_constant but with a pointer to another nir_variable.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3047 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3047 >
2020-02-12 15:41:49 +00:00
Samuel Pitoiset
ddd767387f
aco: fix creating v_madak if v_mad_f32 has two sgpr literals
...
Do not ignore that src1 can be a sgpr.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2435
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3759 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3759 >
2020-02-11 07:17:31 +00:00
Samuel Pitoiset
cd08d9abd7
radv: set the chip name to GCN-NOOP when RADV_FORCE_FAMILY is set
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3654 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3654 >
2020-02-11 07:56:59 +01:00
Samuel Pitoiset
a8024aaaab
radv: make sure to not submit any IBs when RADV_FORCE_FAMILY is set
...
To prevent GPU hangs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3654 >
2020-02-11 07:56:55 +01:00
Bas Nieuwenhuizen
5b335e1599
radv: Do not redundantly set the RB+ regs on pipeline switch.
...
No significant perf changes seen on Bayonetta. (Changes are in the
noise on my Raven Laptop)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3735 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3735 >
2020-02-11 04:39:42 +00:00
Bas Nieuwenhuizen
7792d774e0
radv: Optimize emitting index buffer changes.
...
Since the direct indexed draw packet has the address/count info
inline, there is no sense in emitting the base and size.
No real significant changes found during benchmarks.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3466 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3466 >
2020-02-11 03:07:11 +00:00
Samuel Pitoiset
34fd894e42
aco: fix waiting for scalar stores before "writing back" data on GFX8-GFX9
...
Seems required also on GFX8-GFX9 to achieve correct behaviour. This
is an undocumented behaviour but it makes real sense to me.
pipeline-db on GFX9:
Totals from affected shaders:
SGPRS: 1018 -> 1018 (0.00 %)
VGPRS: 516 -> 516 (0.00 %)
Code Size: 40516 -> 40636 (0.30 %) bytes
Max Waves: 280 -> 280 (0.00 %)
This fixes some sort of sun flickering with Assassins Creed Origins.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2488
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3750 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3750 >
2020-02-10 12:07:25 +00:00
Samuel Pitoiset
4b978cd950
aco: do not use ds_{read,write}2 on GFX6
...
According to LLVM, these instructions have a bounds checking bug.
LLVM only uses them on GFX7+.
This fixes broken geometry in Assassins Creed Origins.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2489
Fixes: 4a553212fahttps://gitlab.freedesktop.org/mesa/mesa/merge_requests/3746 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3746 >
2020-02-07 14:17:06 +01:00
Rhys Perry
ce23911b77
aco: gfx10_wave64_bpermute reduce op to print_ir
...
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3683 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3683 >
2020-02-06 16:43:03 +00:00
Rhys Perry
20eb1acb6f
aco: fix gfx10_wave64_bpermute
...
Since 9254fb4fc79254fb4fc7https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3683 >
2020-02-06 16:43:03 +00:00
Timur Kristóf
4d34abd15c
aco/optimizer: Don't combine uniform bool s_and to s_andn2.
...
Fixes: 8a32f57fffhttps://gitlab.freedesktop.org/mesa/mesa/merge_requests/3714 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3714 >
2020-02-05 22:53:45 +00:00
Bas Nieuwenhuizen
65a6dc5139
radv: Do not set SX DISABLE bits for RB+ with unused surfaces.
...
The extra bits in CB_SHADER_MASK break dual source blending in
SkQP on a Stoney device. However:
- As far as I can tell, some other dual source blend tests are passing
before and after the change.
- A hacked around skqp passes on my Vega desktop and Raven laptop
- Getting Skqp to give any useful info or to run it outside of Android
on ChromeOS is proving difficult.
I have confirmed 3 strategies that seem to work:
- The old radv behavior of setting CB_SHADER_MASK to 0xF
- AMDVLK: CB_SHADER_MASK = 0xFF, and the 3 RB+ regs
are 0.
- radeonsi: CB_SHADER_MASK = 0xFF, but does not set DISABLE
bits in SX_BLEND_OPT_CONTROL for CB 1-7.
Let us use the radeonsi solution as that solution also seems like the correct
thing to do for holes. I have tested on my Raven laptop that setting the high
surfaces to not disabled and downconvert to 32_R does not imply a performance
penalty.
Fixes: e9316fdfd4https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3670 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3670 >
2020-02-04 21:22:30 +00:00
Bas Nieuwenhuizen
d5fd8cd46e
radv: Allow non-dedicated linear images and buffer.
...
Requested for virtualized Vulkan as they need to export memory to
map it.
Since radeonsi and the kernel assume an image without metadata is
linear, this should work just fine.
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3583 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3583 >
2020-02-02 17:47:14 +01:00
Daniel Schürmann
3b323d6601
aco: fix image_atomic_cmp_swap
...
Fixes: 71440ba0f5https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3652 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3652 >
2020-01-31 16:51:46 +00:00
Samuel Pitoiset
0d14f41625
aco: fix MUBUF VS input loads when expanding vec3 to vec4 on GFX6
...
When some unused channels are skipped and that we expand vec3 loads
to vec4 loads, we have to adjust the fourth component.
While we are at it, add an assertion to make sure we don't use
MUBUF for vec3 loads on GFX6.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2450
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2442
Fixes: 6aecc316https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3641 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3641 >
2020-01-31 13:48:56 +01:00
Samuel Pitoiset
3a3b16a395
radv: refactor physical device properties
...
Based on ANV. This removes a bunch of duplicated code for properties.
Fixes: 1b8d99e288https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3626 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3626 >
2020-01-29 21:44:56 +00:00
Timur Kristóf
e73f604b21
aco: Fix the meaning of is_atomic.
...
Previously, is_atomic really meant "is not atomic", contrary to its name.
This commit fixes it to mean what one would think it means.
Fixes: 69bed1c918https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3618 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3618 >
2020-01-29 20:32:31 +00:00
Daniel Schürmann
6f718edced
aco: simplify gathering of MIMG address components
...
This patch has a slight effect on pipelinedb:
Totals from affected shaders:
SGPRS: 23616 -> 21504 (-8.94 %)
VGPRS: 15088 -> 14444 (-4.27 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 662660 -> 664600 (0.29 %) bytes
LDS: 49 -> 49 (0.00 %) blocks
Max Waves: 3079 -> 3204 (4.06 %)
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602 >
2020-01-29 18:45:23 +00:00
Daniel Schürmann
901f06e9ad
aco: simplify adjust_sample_index_using_fmask() & get_image_coords()
...
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602 >
2020-01-29 18:45:23 +00:00
Daniel Schürmann
99d032f3cd
aco: fix register allocation with multiple live-range splits
...
This patch fixes register allocation if multiple live-range splits
occur to the same variable within one instruction.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602 >
2020-01-29 18:45:23 +00:00
Daniel Schürmann
71440ba0f5
aco: reorder VMEM operands in ACO IR
...
For all VMEM instructions, the resource constant is now
in operands[0]. For MIMG instructions, the sampler shares
operands[1] with write data in case this instruction writes memory.
Moving the VADDR to be the last operand for MIMG is the first step to
support Navi NSA encoding.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602 >
2020-01-29 18:45:23 +00:00
