Commit graph

203547 commits

Author SHA1 Message Date
Rob Clark
3d4792d577 freedreno/fdl: Use 4k alignment for tiled
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Tiled-but-not-UBWC images should also have 4k alignment.

Cc: mesa-stable
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40333>
2026-03-12 14:50:11 +00:00
Daivik Bhatia
fcd280f286 v3d/v3dv: drop unused UIF XOR disable plumbing
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uif_xor_disable setup was dropped in commit 2e746bc63d.
This cleans up the remaining code that still uses uif_xor_disable.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40330>
2026-03-12 13:33:46 +00:00
Samuel Pitoiset
f65290f6f9 radv: advertise VK_KHR_copy_memory_indirect on GFX8+
GFX6-7 don't support indirect unaligned dispatches.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37634>
2026-03-12 12:33:04 +00:00
Samuel Pitoiset
99b3f4c7ab radv: implement VK_KHR_copy_memory_indirect
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37634>
2026-03-12 12:33:02 +00:00
Samuel Pitoiset
6b4a04505f radv/meta: make some functions non-static
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37634>
2026-03-12 12:33:02 +00:00
Valentine Burley
b26838ed37 tu: Add support for VK_EXT_depth_clamp_control
Wire up the existing runtime plumbing to the z-clamp registers.

Test: dEQP-VK.draw.*clamp_control*

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40317>
2026-03-12 11:43:02 +00:00
Tapani Pälli
a9ea5825b6 anv: update btp address after CmdExecuteCommands
We need to update state.btp address with the last executed secondary
command buffer btp address so that optimization will work correctly.

Fixes: 8a5ac96a67 ("anv: predicate BTP emissions")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15041
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40361>
2026-03-12 11:17:45 +00:00
Mike Blumenkrantz
20c65db45d zink: run opt_combine_stores when optimizing
this ensures stores to mesh builtins are vectorized, as required by
spec

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40366>
2026-03-12 10:53:32 +00:00
Mike Blumenkrantz
eed3007588 zink: allow renderpass termination for clears with ZINK_DEBUG=rp and GENERAL layouts
this doesn't require a layout change

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40366>
2026-03-12 10:53:32 +00:00
Mike Blumenkrantz
43a6928d62 zink: reapply zsbuf state after unordered blits
this otherwise creates desync if a renderpass continues after blit reordering

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40366>
2026-03-12 10:53:32 +00:00
Samuel Pitoiset
6f12150291 ci: uprev vkd3d
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40319>
2026-03-12 08:14:51 +00:00
Lorenzo Rossi
75425f36dc nir/opt_varyings: Skip code-motion for upconversions
Code-motion should not move back upconversions without any other
instruction, that would only increase memory pressure without any
significant performance benefit (conversions are usually cheap).
This should also help lowering mediump varyings early by not reversing
their work.

Signed-off-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40273>
2026-03-11 23:52:10 +00:00
Paulo Zanoni
b97a1e6870 anv: avoid VK_STRUCTURE_TYPE_BIND_MEMORY_STATUS warnings
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When running "./deqp-vk -n dEQP-VK.memory.binding.maintenance6*", we
get tons of:

    MESA-INTEL: debug: anv_bind_image_memory: ignored VkStructureType
    VK_STRUCTURE_TYPE_BIND_MEMORY_STATUS(1000545002)

The function does not ignore VK_STRUCTURE_TYPE_BIND_MEMORY_STATUS: it
looks for it before the main pNext loop. The pNext loop we have there
calls vk_debug_ignored_stype(), which complains about the fact that
we, allegedly, ignore VK_STRUCTURE_TYPE_BIND_MEMORY_STATUS. Move the
code where we find bind_status to the loop so it doesn't complain
anymore.

Reviewed-by: Iván Briano <ivan.briano@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40351>
2026-03-11 23:14:57 +00:00
Rob Clark
a4cabc1334 freedreno: Add --nvtop arg
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Add a way to generate the table of gpu-ids that nvtop uses, to simplify
syncing nvtop with mesa when new gpu-ids are added.  For example:

  python3 src/freedreno/common/freedreno_devices.py -p ./$builddir/src/freedreno/registers/adreno/ --nvtop

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40283>
2026-03-11 22:20:45 +00:00
Rob Clark
fa90c2de03 freedreno: Split up freedreno_devices.py
Split up the data and code parts.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40283>
2026-03-11 22:20:45 +00:00
Rob Clark
cd1770a077 freedreno: Rename a830
Before it ends up in a release branch.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40283>
2026-03-11 22:20:45 +00:00
Lionel Landwerlin
e20f5a0a7a anv: use companion RCS for hiz ops on compute queue
Fixes new CTS tests.

Similar to a previous change : 5bf3546cc6 ("anv: Use companion cmd
buffer for CCS and MCS image barriers")

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40332>
2026-03-11 21:34:42 +00:00
Mary Guillemard
73dba1e151 nir, nvk, nak: Add base to isbewr_nv and isberd_nv
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On SM86+, we can use a 16-bit unsigned offset along side the register
for it.

This adds a new base indice that will be used for it, integration with
nir_opt_offsets and a lowering pass to get ride of the base on
unsupported generations.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39716>
2026-03-11 19:41:34 +00:00
Mary Guillemard
1a46233a07 nak/nvdisasm_tests: Test ISBERD and ISBEWR
Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39716>
2026-03-11 19:41:34 +00:00
Mary Guillemard
63a9a5e921 nak: Implement ISBEWR and extend ISBERD implementation
ISBERD/ISBEWR allow raw manipulation of the various ISBE spaces
where attributes are stored.

This extends the implementation of ISBERD to support the additional
elements added in its intrinsic and implement ISBEWR intrinsic while
extending the ISBE space sharing detection pass.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39716>
2026-03-11 19:41:34 +00:00
Mary Guillemard
a1996f6985 nak: Legalize ISBERD
This instruction can only take GPRs.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39716>
2026-03-11 19:41:34 +00:00
Mary Guillemard
6a8d09972e nir: Add isbewr_nv intrinsic and extends isberd_nv
Adds a new intrinsic allowing to do raw write in the various ISBE spaces
where attributes are stored.

This also adapt isberd_nv to map to what we have since SM70+.

This will be used to support mesh shaders.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39716>
2026-03-11 19:41:33 +00:00
Marek Olšák
796e1749c6 ac: replace some packet field definitions in sid.h by generated ones
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40183>
2026-03-11 18:54:20 +00:00
Marek Olšák
1c75cd958f ac: enable the new auto-generated CP packet parser
This keeps old packets that were removed from newer HW, packets that set
registers, and packets using non-trivial custom code.

It preserves address checking that was done in print_addr.

Packet names still used the old generator.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40183>
2026-03-11 18:54:20 +00:00
Marek Olšák
c2d01d6fd5 amd: generate a packet parser/printer automatically from packet definitions
The next commit will enable this.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40183>
2026-03-11 18:54:20 +00:00
Marek Olšák
aeab5057a8 amd/packets: remove non-existent CLEAR_STATE from gfx12 definitions
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40183>
2026-03-11 18:54:20 +00:00
Georg Lehmann
07d5c2cbaa radv: set no_signed_zero for FS store_output when format doesn't care
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Or when blending is enabled, because blending doesn't require IEEE math.

Foz-DB Navi21:
Totals from 367 (0.32% of 114627) affected shaders:
MaxWaves: 7884 -> 7876 (-0.10%); split: +0.20%, -0.30%
Instrs: 354948 -> 354386 (-0.16%); split: -0.16%, +0.00%
CodeSize: 1905980 -> 1903172 (-0.15%); split: -0.15%, +0.00%
VGPRs: 20208 -> 20216 (+0.04%); split: -0.08%, +0.12%
Latency: 1855670 -> 1854973 (-0.04%); split: -0.06%, +0.02%
InvThroughput: 540792 -> 539688 (-0.20%); split: -0.20%, +0.00%
PreSGPRs: 18426 -> 18366 (-0.33%)
PreVGPRs: 17213 -> 17249 (+0.21%); split: -0.05%, +0.26%
VALU: 258793 -> 258237 (-0.21%); split: -0.22%, +0.00%
SALU: 35168 -> 35166 (-0.01%); split: -0.01%, +0.01%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40323>
2026-03-11 16:47:15 +00:00
Georg Lehmann
769606e2e6 nir/opt_fp_math_ctrl: handle input/output no_signed_zero flag
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40323>
2026-03-11 16:47:15 +00:00
Georg Lehmann
0d747eee88 nir: add no_signed_zero flag to io semantics
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40323>
2026-03-11 16:47:15 +00:00
Georg Lehmann
26f5a6d6cc nir: fix nir_intrinsic_copy_const_indices for large indices
Fixes: 4ba581887e ("nir: support intrinsic indicies larger than 32 bits")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40323>
2026-03-11 16:47:15 +00:00
Mike Blumenkrantz
c9b2986607 egl/device: fix the fix for explicit sw rejection in non-sw EGL_PLATFORM=device
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"explicit sw" means llvmpipe, which cannot be a real drm device. this requires also
returning only a single device so as to avoid leaking non-sw drivers

should fix LIBGL_ALWAYS_SOFTWARE=1 eglinfo

Fixes: 8a339cdebc ("egl: fix sw fallback rejection in non-sw EGL_PLATFORM=device")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40069>
2026-03-11 16:03:19 +00:00
Job Noorman
5e4a7d01fe ir3: don't predicate vote_all/vote_any
These get lowered to control flow which isn't allowed inside predicated
blocks.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 39088571f0 ("ir3: add support for predication")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40345>
2026-03-11 15:13:07 +00:00
Job Noorman
f88e8b778d ir3: update context builder after ir3_get_predicate
If we are currently inserting instructions after the src of the
predicate conversion, uses of the predicate will be inserted before its
def (the conversion). Fix this by updating the context builder to point
to after the conversion.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: fda91b49d7 ("ir3: refactor builders to use ir3_builder API")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15043
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40336>
2026-03-11 14:19:42 +00:00
Christian Gmeiner
65216acd82 panvk: Implement VK_EXT_memory_budget support
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Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40246>
2026-03-11 08:36:05 +00:00
Samuel Pitoiset
dfdaf6a277 radv: rewrite a comment explaining why PFP waits for ME with streamout
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40327>
2026-03-11 07:34:45 +00:00
Samuel Pitoiset
d9420eed9e radv: fix missing L2 cache invalidation with streamout on GFX12
COPY_DATA emitted from the CP isn't coherent with L2, in case the
buffer filled size needs to be copied.

This fixes rare and random flickering with Mafia 3 Definitive Edition
on RDNA4.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14697
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40327>
2026-03-11 07:34:45 +00:00
Marek Olšák
88a675c1f3 radeonsi: remove AMD_TEST=blitperf
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It's not needed anymore. It has been ported to gpu-ratemeter, improved, and
has Vulkan support.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pelloux@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40311>
2026-03-11 00:08:05 -04:00
Marek Olšák
1c3883bf09 radeonsi: add debug options forcing fast clear, gfx and compute blits
so that we can isolate their performance for gpu-ratemeter

Reviewed-by: Pierre-Eric Pelloux-Prayer <pelloux@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40311>
2026-03-11 00:08:04 -04:00
Marek Olšák
51b2e6f4c2 radeonsi: don't fail si_compute_blit for compressed/subsampled formats properly
Reviewed-by: Pierre-Eric Pelloux-Prayer <pelloux@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40311>
2026-03-11 00:08:02 -04:00
Nanley Chery
eb8883f3ef intel/blorp: Redescribe surfaces for copies
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When copying data between two surfaces, independently increase the size
of each surface's format (bits-per-pixel) as alignment constraints
allow. Adjust the other surface parameters and blorp_copy() parameters
accordingly.

This fixes copies between the 16bpp YCRCB formats and 32bpp formats:
dEQP-VK.ycbcr.single_plane_copy.linear.linear.r8g8b8a8_to_g8b8g8r8_422
This new test failure was reported by Iván Briano.

More generally, this increases the efficiency of our copies. As shown in
the configuration pages of the PRMs, our sampler is able to fetch texels
at a fixed rate of texels / clock regardless of the texel size
(presumably our rendering hardware has similar behavior). By using the
largest texel size possible, we can transfer more bits / clock.

Improves the performance of a number of traces in the performance CI for
BMG:

* TotalWarWarhammer3 +2.24%
* Payday3 	     +1.87%
* BaldursGate3 	     +1.34%
* Control 	     +1.25%
* TotalWarPharaoh    +1.22%

Four additional traces are helped between +0.44% and +0.96%.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39974>
2026-03-11 00:36:19 +00:00
Nanley Chery
73796c7245 intel/blorp: Add blorp_surf_convert_to_single_level_tile()
Convert a Tile64/Yf/Ys surface to a single level or a single miptail.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39974>
2026-03-11 00:36:19 +00:00
Nanley Chery
9351dbfb25 intel/blorp: Use stencil hardware less for CPB copies
Don't use it without ISL_AUX_USAGE_STC_CCS. With a future patch, this
will allow blorp_copy() calls to increase the size of the surface format
for CPB.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39974>
2026-03-11 00:36:19 +00:00
Nanley Chery
20bf27f2a8 intel/blorp: Make blorp_copy() format queries aux-dependent
blorp_copy() will soon start changing the format in a way which drivers
cannot rely on to do things like manage the texture cache (see iris).

Narrow down the scope of blorp_copy_get_formats() and
blorp_copy_get_color_format() such that the returned value can only be
trusted if compression would be enabled on each image.

By doing this (and adapting iris to reflect this), we'll get the
required flushes on the platforms which need
WaSamplerCacheFlushBetweenRedescribedSurfaceReads:

* On the platforms which need the workaround for all formats,
  blorp_copy() will stick with the queried format on compressed
  surfaces.
* On the platforms which need the workaround when switching from ASTC
  and non-ASTC formats, blorp_copy() may actually change the queried
  format on compressed surfaces. This is not a problem, because
  surfaces which may be read with ASTC formats are not compressible.

Prevents gfx9 from failing tests under:
* KHR-GL46.copy_image.functional_src_target_texture_2d_array_src_format_r3_g3_b2*
* KHR-GL46.copy_image.functional_src_target_texture_2d_array_src_format_rgb5*
* KHR-GL46.copy_image.functional_src_target_texture_2d_array_src_format_rgba2*
* KHR-GL46.copy_image.functional_src_target_texture_2d_array_src_format_rgba4*

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39974>
2026-03-11 00:36:18 +00:00
Nanley Chery
7fffd67803 anv: Add WaSamplerCacheFlushBetweenRedescribedSurfaceReads
With upcoming blorp_copy() changes, this avoids the following failures
with zink on gfx9:
* dEQP-GLES3.functional.texture.specification.basic_teximage3d.r8_2d_array
* dEQP-GLES3.functional.texture.specification.basic_teximage3d.r8_snorm_2d_array
* dEQP-GLES3.functional.texture.specification.basic_teximage3d.r8i_2d_array
* dEQP-GLES3.functional.texture.specification.basic_teximage3d.r8ui_2d_array

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39974>
2026-03-11 00:36:18 +00:00
Nanley Chery
465c186fc5 anv: Prepare for format width changes in blorp_copy()
blorp_copy() will soon gain the ability to increase the format bpb.
Prepare anv by replicating the clear color pixel on gfx12.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39974>
2026-03-11 00:36:18 +00:00
Nanley Chery
d993e0dc47 intel/blorp: Add blorp_surf::has_replicated_pixel
This allows blorp_copy() to widen a surface format width in some cases.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39974>
2026-03-11 00:36:17 +00:00
Nanley Chery
a77f79f21e intel/blorp: Lower bit-casting code in blorp_copy()
We're going to add code between calling
blorp_surf_convert_to_uncompressed() and bit-casting determination.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39974>
2026-03-11 00:36:17 +00:00
Nanley Chery
e0859f5ca1 intel/isl: Use a fixed alignment for single slices
We're going to start changing the surface format during blorp_copy().
Changing the surface format could lead to incorrect image alignment
parameters, so return a fixed halign and valign for images with a single
subresource. That's all that will be needed for the upcoming
blorp_copy() changes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39974>
2026-03-11 00:36:17 +00:00
Nanley Chery
b16b9b5591 intel/isl: Relax some alignments in get_image_surf()
Aux-tt alignment only applies to the beginning of the resource. Drop it
if we're pointing to an image that is not in the first tile of the
image. Likewise for the alignment we add for sequential multi-engine
access.

We allow sparse on 1D images. When getting an image from such a surface,
the alignment likely won't be aligned to 64KB. So, in this case, remove
the flag to avoid the alignment expectation.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39974>
2026-03-11 00:36:16 +00:00
Nanley Chery
8d82d06cbc intel/isl: Generalize and move some Yf/Ys miptail limits
Increase the scope of Yf/Ys miptail workarounds to drop the dependency
on format type (compressed or uncompressed) and make this information
more publically accessible. If I recall correctly, the affected tests
only performed blorp_copy() uploads and downloads and never accessed
images with compressed formats. So, we likely should be increasing the
scope.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39974>
2026-03-11 00:36:16 +00:00