Commit graph

10998 commits

Author SHA1 Message Date
Tapani Pälli
36f428f1de anv: check for wa 16013994831 in emit_so_memcpy_end
We are toggling preemption on/off during streamout, this is also
happening on gfx12 platforms, not just dg2.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27002>
2024-01-15 08:36:29 +00:00
Vinson Lee
73835874a8 intel/disasm: Remove duplicate variable reg_file
Fix defects reported by Coverity Scan.

Evaluation order violation (EVALUATION_ORDER)
write_write_typo: In reg_file = reg_file = brw_inst_dpas_3src_dst_reg_file(devinfo, inst),
reg_file is written twice with the same value.

Fixes: 1c92dad5cb ("intel/disasm: Disassembly support for DPAS")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27056>
2024-01-15 07:46:12 +00:00
Lionel Landwerlin
ff6041afdf intel/aux_map: fix fallback unmapping range on failure
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7c6faa1efe ("intel/aux_map: introduce ref count of L1 entries")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27057>
2024-01-15 08:08:21 +02:00
José Roberto de Souza
49fe060b5f anv: Fix PAT entry for userptr in integrated GPUs
Fixes: 060439bdf0 ("anv: Add ANV_BO_ALLOC_IMPORTED")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27040>
2024-01-12 21:32:49 +00:00
Caio Oliveira
1a31970946 intel/compiler/xe2: Implement instruction compaction for DPAS.
These use different tables but map to the same bits, so it is just
a matter of picking the right tables for the instruction.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
6e56a4b474 intel/compiler/xe2: Fix for the removal of AccWrCtrl.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
7f39e51dd5 intel/compiler/xe2: Add extra flag registers.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
f974eacab3 intel/compiler/xe2: Fix for the removal of most predication modes.
Reworks:
* Remove changes to fixup_nomask workaround since it applies only for
  Gfx12 family.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
f79123e1d9 intel/compiler/xe2: Fix for NibCtrl field removal.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
7db3f0b1c1 intel/compiler/xe2: Implement instruction compaction.
Reworks:
* Handle DPAS in has_3src_unmapped_bits.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
57ba9c176c intel/compiler/xe2: Implement codegen of compact instructions.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
d8ba1d63bc intel/compiler: Add assume() checks to brw_compact_inst_(set_)bits().
Similar to the preconditions of brw_inst_(set_)bits().

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
4a24f49b57 intel/compiler/xe2: Implement codegen of three-source instructions.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
e10e7d5aa3 intel/compiler/xe2: Implement codegen of indirect immediates.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
294bdbb253 intel/compiler/xe2: Implement codegen of 2-source instruction operands.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
72bbfa8e8d intel/compiler/xe2: Implement codegen of general instruction controls.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Francisco Jerez
066e6c6234 intel/compiler/xe2: Add Xe2 bounds to FF() macro.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860>
2024-01-12 20:18:03 +00:00
Tapani Pälli
810c1f7747 hasvk: remove gfx9 specific cs stall from emit_ps_depth_count
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26997>
2024-01-12 14:01:08 +00:00
Tapani Pälli
30c148fd16 hasvk: remove softpin (GFX_VERx10 >= 90) related code
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26997>
2024-01-12 14:01:08 +00:00
Tapani Pälli
ed2743258a hasvk: remove gfx9 specific code from emit_sample_pattern
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26997>
2024-01-12 14:01:08 +00:00
Tapani Pälli
4d3d3a495f hasvk: remove cmd_buffer_ray_query_globals function decl
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26997>
2024-01-12 14:01:08 +00:00
Rohan Garg
91798bab2d anv: refactor emit_dynamic_buffer_binding_table_entry
Refactor emit_dynamic_buffer_binding_table_entry to emit a null surface
state when the descriptor has no assocaited buffers allowing us to drop
the same check elsewhere.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27005>
2024-01-12 11:55:41 +00:00
José Roberto de Souza
475661a64e intel/isl/xe2: Disable route of Sampler LD message to LSC
This optimization is causing some tests groups to fail, like:
dEQP-VK.image.mutable.2d_array.*
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.*

So disabling it until properly fixed.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27016>
2024-01-12 01:51:59 +00:00
Francisco Jerez
ae29ffb637 intel/eu/gfx12.5+: Don't fail validation with ARF register restriction error for indirect addressing.
The "file" field doesn't exist for indirect operands, so it contains
garbage.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26994>
2024-01-12 00:20:38 +00:00
Francisco Jerez
32b3ea3c3d intel/eu/validate: SEND instructions don't have immediate encodings on Gen12+.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26994>
2024-01-12 00:20:38 +00:00
Francisco Jerez
dfb034853a intel/fs: Use full 32-bit sample masks when immediate.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26994>
2024-01-12 00:20:38 +00:00
Lionel Landwerlin
695b4a2992 anv: fix disabled Wa_14017076903/18022508906
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: d0669f3ede ("intel/dev: switch defect identifiers to use lineage numbers")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27008>
2024-01-11 23:36:05 +00:00
Emma Anholt
920fe469b3 ci: Disable VK full runs that time out since 1.3.7.0 (hasvk, anv-tgl, a630)
Even the ESO fixes aren't helping, so just disable them for now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25922>
2024-01-11 22:45:05 +00:00
Lionel Landwerlin
62c21c240e anv: remove ANV_ENABLE_GENERATED_INDIRECT_DRAWS variable
We have a threshold drirc value & environment variable.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26967>
2024-01-10 18:32:24 +00:00
Tapani Pälli
29fc135a55 anv: use workaround framework for Wa_22018402687
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26925>
2024-01-10 08:26:41 +00:00
José Roberto de Souza
ad158b0bee anv: Call anv_measure_submit() before anv_cmd_buffer_chain_command_buffers()
Otherwise the measurement instructions will be placed after the
MI_BATCH_BUFFER_START calling the next cmd_buffer.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882>
2024-01-09 14:28:19 +00:00
José Roberto de Souza
d37414d8a4 anv: Fix anv_measure_start/stop_snapshot() over copy or video engine
Those engines don't have PIPE_CONTROL so we can't do
ANV_TIMESTAMP_CAPTURE_AT_CS_STALL but we can support measurement
by changing the capture type to ANV_TIMESTAMP_CAPTURE_TOP/END_OF_PIPE

Right now this issue is only reproduced in Xe KMD without setting
any special parameters(other than INTEL_MEASURE) because Xe KMD allows
the usage of copy engine while i915 can't due TRTT restrictions.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882>
2024-01-09 14:28:19 +00:00
José Roberto de Souza
b8d48ebc93 anv: Add missing anv_measure_submit() calls in Xe KMD backend
Without this intel_measure don't work with Xe KMD.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882>
2024-01-09 14:28:19 +00:00
José Roberto de Souza
a0f7820fe8 anv: Simply companion_rcs handling
Here dropping is_companion_rcs_cmd_buffer parameter of a few functions
that don't need this information, it just need the right
anv_cmd_buffer for each case.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882>
2024-01-09 14:28:18 +00:00
José Roberto de Souza
428a179865 anv: Drop useless STATIC_ASSERT in anv_physical_device_init_queue_families()
assert(family_count <= ANV_MAX_QUEUE_FAMILIES) already takes care
of STATIC_ASSERT without need of updates.

Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882>
2024-01-09 14:28:18 +00:00
José Roberto de Souza
0997766069 anv: Increase ANV_MAX_QUEUE_FAMILIES
If ANV_VIDEO_DECODE, ANV_VIDEO_DECODE and INTEL_COPY_CLASS are enabled
it is possible to have 5 different queues, so here increasing
ANV_MAX_QUEUE_FAMILIES.

Fixes: 17b8b2cffd ("anv: Add support for a transfer queue on Alchemist")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882>
2024-01-09 14:28:18 +00:00
Sviatoslav Peleshko
8e6d28f473 intel/tools/tests: Add i965_asm tests for gfx12 and gfx12.5
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
b87fc2125e intel/tools/tests: Unbreak i965_asm tests
Currently it's searching for test cases in the nonexistent folders, and
because there are none, tests always pass. Point the script onto the
correct ones. And while we're at it, add a check to make sure this
situation won't repeat in the future.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
bb2083a57c intel/tools/tests: Fix sends indirect argument in gfx9 test
Currently it's in the wrong format. It was fixed in disasm in
98aab272 ("intel/disasm: Properly disassemble indirect SENDs").
This was accidentally working previously, but isn't accepted after the
changes made to implement send on gfx12.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
98d2461424 intel/tools/i965_asm: Don't set src0 for break and while on gfx12
This effectively implements same changes as were done to codegen in
bafc9515 ("intel/eu/gen12: Codegen control flow instructions correctly.")

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
db4d58fe31 intel/tools/i965_asm: Add dp4a and add3 instructions
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
88fcd305be intel/tools/i965_asm: Implement gfx12 and gfx12.5 send/sendc
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
bc46cc7807 intel/tools/i965_asm: Allow src0 and src2 of ternary instructions to be imm
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
8eaa0db13f intel/tools/i965_asm: Don't override flag reg from cond modifier
Both predication and conditional modifier use the same flag, but in
assembly it's specified only once. If the instruction already has a
flag from predication we should not override it with zeroes.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
f96e08f34d intel/tools/i965_asm: Allow neg and abs modifiers on accumulator register
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
98665e024f intel/tools/i965_asm: Handle sync instruction
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
9dd3a6f86f intel/tools/i965_asm: Handle HF immediates
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
0c41a8f5d6 intel/tools/i965_asm: Add SWSB handling
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
cfb34dc695 intel/eu/validate: Validate that the ExecSize is a factor of chosen ChanOff
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
dbf6f0291a intel/fs: Set group 0 for Wa_14010017096 MOV instruction
We always set exec size to 16 for this MOV, but the execution group remains
from the previous emitted instruction. This can cause emitting a group
which violates PRM restriction for ChanOff: "The execution size (ExecSize)
must be a factor of the chosen offset."

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
2024-01-09 11:35:52 +00:00