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Author SHA1 Message Date
Samuel Pitoiset
36768eee9a radv/sqtt: do not assume that the number of shader engines is 4 
It's not always 4, for example on RAVEN there is only one.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4018>
 2020-03-02 12:23:35 +01:00
Samuel Pitoiset
1b565e56e9 radv/rgp: adjust trace memory/shader clocks to fix frame duration 
To report microseconds instead of clocks.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4018>
 2020-03-02 12:23:33 +01:00
Tapani Pälli
fbd61b3fb6 mesa/st: fix formats required for EXT_texture_norm16 
Earlier commit did not take in to account that lists required for
rendering and texturing are parsed separately. This commit simply
removes formats added to the other list.

Fixes: de4eb9a3bb ("mesa/st: toggle EXT_texture_norm16 based on format support")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3961>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3961>
 2020-03-02 10:53:44 +00:00
Andreas Baierl
e58bb417b5 lima: Add etc1 support 
Layer stride has to be divided by 4. We also have to take care of
the array_size when returning the bo_size.

Drop the affected tests from the fails list.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3946>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3946>
 2020-03-02 10:33:06 +00:00
Lionel Landwerlin
85457e350d intel/tools/dump_gpu: fix getparam values 
Don't return the pci_id for all params

Fixes: 76bf38eaf0 ("intel/tools/aub_dump: move aub file initialization to maybe_init()")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3994>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3994>
 2020-03-02 08:24:40 +00:00
Ilia Mirkin
5306b662dd mesa: fix _mesa_draw_nonzero_divisor_bits to return nonzero divisors 
The bitmask is _EffEnabledNonZeroDivisor, so no need to invert it before
returning.

Fixes: fd6636ebc0 (st/mesa: simplify determination whether a draw needs min/max index)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4009>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4009>
 2020-03-01 23:16:36 +00:00
Samuel Pitoiset
02f3af2ad1 radv: fix size of sqtt_file_chunk_asic_info on 32-bit system 
The struct is actually 716 bytes, but on 64-bit systems the compiler
aligns it to 720. Add padding to make sure it's always 720.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2580
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2578
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3996>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3996>
 2020-02-29 05:54:54 +00:00
Samuel Pitoiset
33f604a331 radv: fix 32-bit build failure in radv_queue_internal_submit() 
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2580
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2578
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3996>
 2020-02-29 05:54:54 +00:00
Timothy Arceri
ad094433b4 glsl: add some error checks to the nir uniform linker 
These are optional for spirv but it shouldnt hurt to enable them.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
 2020-02-28 23:48:46 +00:00
Timothy Arceri
61dc9354c0 glsl: fix sampler index calculation in nir linker 
Here we reset the counter to 0 for each shader stage not each program.
We also make add a flag to stop iterating over indices that have
already been processed.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
 2020-02-28 23:48:46 +00:00
Timothy Arceri
ef47069cc3 glsl: reset next_image_index count for each shader stage 
This fixes the image index calculation in the nir linker. We need
to reset the counter to 0 for each shader stage not each program.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
 2020-02-28 23:48:46 +00:00
Timothy Arceri
e0aa0a839f glsl: fix resizing of the uniform remap table 
In the NIR linker we were not resizing the remap table correctly
for explicit locations when it was needed.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
 2020-02-28 23:48:46 +00:00
Timothy Arceri
190a1ed170 glsl: set the correct number of images in a shader 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
 2020-02-28 23:48:46 +00:00
Timothy Arceri
b232a54df1 glsl: set the correct number of samplers in a shader 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
 2020-02-28 23:48:46 +00:00
Timothy Arceri
7dafc3050d glsl: fix possible memory leak in nir uniform linker 
Use UniformDataSlots for the context of UniformDataDefaults rather
than UniformStorage as in some cause UniformStorage may be NULL.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
 2020-02-28 23:48:46 +00:00
Jordan Justen
cf12faef61
intel/compiler: Restrict cs_threads to 64 
Our current GPGPU_WALKER code only supports up to 64 threads.

On HSW we could use up to 70 and TGL up to 112, but only if the walker
is adjusted so the width does not exceed 64. Work to support this is
in progress.

Previous to this change, we might try to downgrade to SIMD8 if the
SIMD16 shader spilled. Since HSW and TGL have the max number of
threads above 64, we would then try to emit an invalid GPGPU walker
command.

Fixes: 932045061b ("i965/cs: Emit compute shader code and upload programs")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
 2020-02-28 14:45:43 -08:00
Thong Thai
0932363489 st/va: remove unneeded code 
No need to explicitly set the 10-bit buffer format as the correct
buffer format will be allocated later

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3998>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3998>
 2020-02-28 20:16:38 +00:00
Rob Clark
8cb9f79413 freedreno/ir3: add assert 
Catch problems earlier when inputs are not setup correctly.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:41 +00:00
Rob Clark
ac705edd82 freedreno/ir3: fix assert with getinfo 
Fixes:
dEQP-VK.glsl.texture_functions.query.texturesamples.sampler2dms_fixed_vertex

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:41 +00:00
Rob Clark
c1f4367461 freedreno/ir3: don't precolor unassigned inputs 
Fixes crash seen in:
dEQP-VK.glsl.conversions.matrix_to_matrix.mat4_to_mat3x4_vertex

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:41 +00:00
Rob Clark
4b8e198fd2 freedreno/ir3: fix crash with samgq workaround 
Need to list_delinit() before we clone the instruction to split it into
individual samgpN instructions, otherwise we get list corruption.

Tested-by: Eduardo Lima Mitev <elima@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:41 +00:00
Rob Clark
56565b7bba freedreno/ir3: update SFU delay 
1) emperically, 10 seems like a more accurate # than 4
2) push "soft" delay handling into ir3_delayslots(), as
   we should also be using it to calculate the costs
   that the schedulers use

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:41 +00:00
Rob Clark
2cf4b5f29e freedreno/ir3: track half-precision live values 
In schedule live value tracking, differentiate between half vs full
precision.  Half-precision live values are less costly than full
precision.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:41 +00:00
Rob Clark
4353b3c1c5 freedreno/ir3: don't hide latency when there is none to hide 
Current scheduler thresholds try to ensure there are warps available to
switch to when hiding texture fetch latency.  But if there is none to
hide, we should allow scheduler to use more registers to reduce nops.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:41 +00:00
Rob Clark
9d2aaa589c freedreno/ir3: rewrite regmask to better support a6xx+ 
To avoid spurious sync flags, we want to, for a6xx+, operate in terms of
half-regs, with a full precision register testing the corresponding two
half-regs that it conflicts with.

And while we are at it, stop open-coding BITSET

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:41 +00:00
Rob Clark
c02cd8afbd freedreno/ir3: remove regmask_set_if_not() 
No longer used.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:41 +00:00
Rob Clark
2fa64729db freedreno: honor FD_MESA_DEBUG=nogrow 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:41 +00:00
Rob Clark
bab9db6c02 freedreno/a6xx: enable SKIP_IB2_ENABLE properly 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:40 +00:00
Rob Clark
9724a7c105 freedreno/a6xx: don't emit YIELD packet 
We don't implement the rest of this.. and it would probably cause bad
things when kernel gains support for preemption.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:40 +00:00
Rob Clark
45771786e4 freedreno/a6xx: whitespace fix 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:40 +00:00
Rob Clark
ae3e237db0 freedreno/a6xx: emit LRZ clear in sysmem too 
Fixes rendering issues in manhattan with FD_MESA_DEBUG=nogmem

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:40 +00:00
Rob Clark
6b605804ea freedreno/a6xx: remove unused param 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:40 +00:00
Rob Clark
141d0d1c25 freedreno/ir3: remove from_tgsi 
No longer used, other than in ir3 cmdline compiler, where it can be
replaced with a local variable.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
 2020-02-28 16:53:40 +00:00
Jonathan Marek
c7ac1bcea0 turnip: increase array sizes in tu_descriptor_map 
Pending the descriptor rework, this allows running the follow test:
dEQP-VK.renderpass.suballocation.attachment_sparse_filling.input_attachment_127

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
 2020-02-28 14:04:20 +00:00
Jonathan Marek
d195eef05d turnip: fall back to sysmem when attachments don't fit into gmem 
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
 2020-02-28 14:04:20 +00:00
Jonathan Marek
de3230e0a5 turnip: remove unnecessary fb size check 
Framebuffer with 0 width or height is not valid.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
 2020-02-28 14:04:20 +00:00
Jonathan Marek
cf302c9a22 turnip: don't hardcode gmem base for input attachment 
Newer a6xx no longer has programmable GMEM base, so we can't rely on the
kernel driver setting it to 0x100000 (GMEM base is 0 on such GPUs).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
 2020-02-28 14:04:20 +00:00
Jonathan Marek
6420406f19 turnip: fix srgb MRT 
Register packing macros makes this only set the first bit. Set to whole
dword to fix srgb for color attachments >0.

Fixes: 59f29fc8 ("turnip: Convert the rest of tu_cmd_buffer.c over to the new pack macros.")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
 2020-02-28 14:04:20 +00:00
Jonathan Marek
8f9e1c6047 turnip: fix hw binning + render_area offset interaction 
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
 2020-02-28 14:04:20 +00:00
Jonathan Marek
de33c23370 turnip: minify image_view extent 
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
 2020-02-28 14:04:20 +00:00
Jonathan Marek
b18d6575fe turnip: remove unecessary MRT_CONTROL fill 
Hardware won't use MRT_CONTROL after mrt_count

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
 2020-02-28 14:04:20 +00:00
Jonathan Marek
33b2db5fb9 turnip: move some constant state to tu6_init_hw 
Also remove duplicates.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
 2020-02-28 14:04:20 +00:00
Jonathan Marek
7d27a9ffb3 turnip: check the right alignment requirement on shader iova 
I had some trouble because I assumed this was right, tested that the
alignment requirement is actually 16.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
 2020-02-28 14:04:20 +00:00
Jonathan Marek
0f0662a551 turnip: add r5g5b5a1_unorm/b5g5r5a1_unorm formats 
r5g5b5a1/b5g5r5a1 tiled/ubwc is the same as a1r5g5b5 (in memory), but
linear is read as 1_5_5_5 and written with 5_5_5_1 with swap.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806>
 2020-02-28 12:48:11 +00:00
Jonathan Marek
80ceebcdd1 turnip: rework format table to support r5g5b5a1_unorm/b5g5r5a1_unorm 
These formats are an exception that can't be modeled in the current format
table. Switch to a table with only a single a6xx_format per vk format,
and deal with the exceptions separately (currently the only exception is
10_10_10_2_UNORM which has a different color format).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806>
 2020-02-28 12:48:11 +00:00
Jonathan Marek
89c6ef4233 util/format: add missing BC4/BC5 vulkan formats 
Enables these formats for turnip.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806>
 2020-02-28 12:48:11 +00:00
Icecream95
339f127f2b panfrost: LogicOp fixes and non 8-bit format support 
With the previous LogicOp commit almost half of the blend modes were
broken because the surplus bits were not cleared after an inot.

v2:
 - Remove u8 "fast path" as 8-bit is not well optimised yet
 - Don't mask for 32-bit formats as that triggers an assert

Fixes: 068806c9f6 ("panfrost: LogicOp support")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3943>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3943>
 2020-02-28 11:52:40 +00:00
Icecream95
574b03eebf nir: Allow nir_format conversions to work on 32-bit values 
The constant has to changed to unsigned long long, as shifting a
32-bit value by 32 is undefined behaviour.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3943>
 2020-02-28 11:52:40 +00:00
Greg V
cf69b9635a r600: add missing <array> include 
Fixes error with clang/libc++:

../src/gallium/drivers/r600/sfn/sfn_emitaluinstruction.h:69:88: error: implicit instantiation of undefined template 'std::__1::array<unsigned char, 3>'
   bool emit_alu_op3(const nir_alu_instr& instr, EAluOp opcode, std::array<uint8_t, 3> reorder={0,1,2});

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3967>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3967>
 2020-02-28 11:30:39 +00:00
Dave Airlie
eb5227173f llvmpipe: add support for tessellation shaders 
This adds the hooks between llvmpipe and draw to enable tessellation shaders.

It also updates the CI results and docs.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
 2020-02-28 18:33:34 +10:00