Gert Wollny
24a02157dd
i965: Correct L8_UNORM_SRGB table entry
...
As the name says, the format is an sRGB format.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-19 08:05:44 +01:00
Jason Ekstrand
8152c60e01
intel/isl/format: Get rid of the ALPHA colorspace
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Alpha-only formats are just linear. There's no need to specially
deliminate them as being in their own colorspace.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-05-09 11:16:33 -07:00
Jason Ekstrand
96598fbc02
intel/isl/format: Add a column for channel order to the table
...
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-05-09 11:16:33 -07:00
Lionel Landwerlin
42a8fd1670
isl: fill out layout descriptions for yuv formats
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Some description was missing.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-06 11:45:52 +01:00
Nanley Chery
52a6fd9871
intel/isl: Add ASTC HDR to format lists and helpers
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Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2017-05-22 11:13:53 -07:00
Jason Ekstrand
3ab3d97ac9
isl: Add support for color control surfaces
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Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-13 11:47:37 -07:00
Jason Ekstrand
219024b9a7
isl: Add support for multisample compression surfaces
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Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-13 11:47:37 -07:00
Jason Ekstrand
33dc8549fb
isl: Add support for HiZ surfaces
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Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-13 11:47:37 -07:00
Jason Ekstrand
324103da75
isl/format: Mark R9G9B9E5 as containing 9-bit unsigned float channels
...
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-06-22 12:26:43 -07:00
Jason Ekstrand
03a82dc5d1
isl: Add the ISL_FORMAT_R32G32_FLOAT_LD format
2016-05-23 19:12:34 -07:00
Nanley Chery
de86fb875d
isl: Add 2D ASTC format layouts and enums
...
Also, make changes needed for successful compilation and registration
as a texture compression mode.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-20 09:27:11 -07:00
Jason Ekstrand
47b8b08612
Move isl to src/intel
2016-02-18 10:34:47 -08:00
