Commit graph

71601 commits

Author SHA1 Message Date
Martin Roukala (né Peres)
33232223f6 zink/ci: update the expectations of RADV-based pre-merge jobs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37934>
2025-10-20 10:30:51 +00:00
Jose Maria Casanova Crespo
a131530dd1 v3d: mark FRAG_RESULT_COLOR as output_written on SAND blits FS
With the introduction of "v3d: Add support for 16bit normalised
formats" https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35820
nir_lower_fragcolor is always called if shaders outputs_written shows
that FRAG_RESULT_COLOR is used.

But on SAND8/30 blit fragment shaders although the FRAG_RESULT_COLOR
is used, it was not marked as output_written so the lowering was not
applied.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14141
Fixes: ee48e81b26 ("v3d: Always lower frag color")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37949>
2025-10-20 09:42:19 +02:00
Marek Olšák
e2b271d7b1 radeonsi/ci: update hawaii failures
Some checks are pending
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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37910>
2025-10-19 17:01:44 +00:00
Marek Olšák
f5b648f6d3 winsys/radeon: fix completely broken tessellation for gfx6-7
The info was moved to radeon_info, but it was only set for the amdgpu
kernel driver. It was uninitialized for radeon.

Fixes: d82eda72a1 - ac/gpu_info: move HS info into radeon_info

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37910>
2025-10-19 17:01:43 +00:00
Qiang Yu
11f2babddc mesa,gallium: not touch TS when internal draws
Some checks are pending
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TS does not affect vertex pipeline draws. We keep mesh shader
before radeonsi is ready.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:19 +00:00
Qiang Yu
4711fb711c gallium/blitter: no need to save TS state
TS does not affect blitter currently.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:19 +00:00
Qiang Yu
71e0895715 mesa,radeonsi: add comments about vertex and mesh pipeline shader states
They are exclusive in mesa state tracker currently, so add some comments
and assertions for developers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:19 +00:00
Qiang Yu
dcf2399e6f radeonsi: save mesh shader when blit
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:19 +00:00
Qiang Yu
ffc3d430db radeonsi: simplify si_update_rasterized_prim while handle mesh shader
Otherwise mesh shader ends in the "else" section.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:19 +00:00
Qiang Yu
56a437183a radeonsi: si_get_vs support mesh shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:19 +00:00
Qiang Yu
7e83962e85 radeonsi: update scratch va for mesh shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:19 +00:00
Qiang Yu
de4fb088d3 radeonsi: share some vertex pipe function with mesh pipe
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:18 +00:00
Qiang Yu
e6e21dfbf2 radeonsi: kill outputs for mesh shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:18 +00:00
Qiang Yu
4c315bdbfa radeonsi: lower task/mesh shader io to mem
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:18 +00:00
Qiang Yu
5931dbf7ac radeonsi: add task info to screen
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:18 +00:00
Qiang Yu
73aebeec42 radeonsi: no ngg culling for mesh shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:17 +00:00
Qiang Yu
74894150f1 radeonsi: init pm4 state for mesh shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:17 +00:00
Qiang Yu
ce6a1e7563 radeonsi: init mesh shader args
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:16 +00:00
Qiang Yu
2038134efc radeonsi: calc workgroup size for mesh shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:15 +00:00
Qiang Yu
977a3f45bf radeonsi: add task/mesh shader info to si_shader_info
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:15 +00:00
Qiang Yu
8659666089 radeonsi: add si_mesh_resources_add_all_to_bo_list
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:14 +00:00
Qiang Yu
b533d39b95 radeonsi: inline uniform support mesh shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:14 +00:00
Qiang Yu
8a3ef188c2 radeonsi: add context shader state for mesh shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:13 +00:00
Qiang Yu
24d7c9a2a8 radeonsi: handle mesh shader when si_create_shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:12 +00:00
Qiang Yu
f06a1b0d07 radeonsi: enlarge SI_NUM_SHADERS for mesh shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
2025-10-17 03:52:12 +00:00
Mike Blumenkrantz
f74cf45078 zink: consistently set/unset msrtss in begin_rendering
Some checks are pending
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this has to always be set or unset, never persistent from previous renderpass

Fixes: 5080f2b6f5 ("zink: disable msrtss handling when blitting")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37923>
2025-10-16 22:22:34 -04:00
Marek Olšák
733ba77bfe r300: fix DXTC blits
Some checks are pending
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Fixes: 9d359c6d10 - gallium: delete pipe_surface::width and pipe_surface::height
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37912>
2025-10-16 22:33:50 +00:00
Gert Wollny
ba35ac29b6 r600/sfn: drop range pinning for registers after RA
Some checks are pending
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Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37847>
2025-10-16 20:57:18 +00:00
Gert Wollny
5962add398 r600/sfn: correct register interference range
If a life range of one register starts in the same instruction where the
life range of another register ends, then
the two ranges don't overlap.

v2: Fix test

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37847>
2025-10-16 20:57:18 +00:00
Mary Guillemard
b2accf86d1 poly: Migrate AGX's GS/TESS emulation to common code
This moves most of the code to a new home: src/poly.
Most precomp kernels logic that could be moved are provided by poly now.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
2025-10-16 19:25:35 +00:00
Mary Guillemard
60e5abdbaa asahi: Move compiler preprocess out of agx_nir_lower_gs
We run agx_preprocess_nir as the last step of each new compute shaders
in agx_nir_lower_gs but we could move this out of the pass and makes it
the driver responsability to call it.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
2025-10-16 19:25:35 +00:00
Mary Guillemard
71c4943c37 compiler: rename vs.tes_agx bit to vs.tes_poly
Preparing to move AGX's GS/TESS lowering code.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
2025-10-16 19:25:35 +00:00
Mary Guillemard
1e0c18d6cf nir: Rename stat_query_address_agx to stat_query_address_poly
This is used by the geometry lowering that we are going to move to
common code.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
2025-10-16 19:25:35 +00:00
David Rosca
09ff0fa005 frontends/va: Move remainig processing functions to postproc.c
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37545>
2025-10-16 16:33:15 +00:00
David Rosca
7a5270d4df frontends/va: Move decode functions to separate file
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37545>
2025-10-16 16:33:15 +00:00
David Rosca
ba0a059129 frontends/va: Move encode functions to separate file
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37545>
2025-10-16 16:33:15 +00:00
Gert Wollny
a2e4280dbe r600/sfn: drop unused code
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37846>
2025-10-16 15:36:55 +00:00
Gert Wollny
0f7dd6636c r600/sfn: rework 64 bit to vec2 32 bit lowering
The old lowering was quite messy and didn't work well if
64 bit registers were involved.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37846>
2025-10-16 15:36:55 +00:00
Utku Iseri
39ac7df612 panfrost,panvk: distinguish fbd bounding box from framebuffer size
On panvk, we can use the render area to set fbd bbox extents
instead of setting them based on image sizes. Doing this improves
partial updates (eg. loadOp:load with renderArea < image_size) of
AFBC render targets.

This commit introduces a new structure for this setting and uses
it on both panvk and panfrost. We can't reuse the existing extent
here as that is based on viewport+scissor, which can change within
a renderpass/batch, which causes issues on panfrost.

No functional changes for panfrost, as it doesn't have an equivalent
to renderpass::renderArea so we can't do the same thing there, it
still uses the entire framebuffer extent.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37771>
2025-10-16 13:28:37 +00:00
Utku Iseri
bde9156dcf panfrost,panvk: rename pan_fb_info::extent to draw_extent
This represents what this bounding box is being used for better,
as it can be easily confused with the framebuffer bounding box
otherwise.

Also fixes the comment about inclusiveness, as these are being
used as exclusive on both panfrost and panvk.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37771>
2025-10-16 13:28:37 +00:00
Samuel Pitoiset
abcaa46f6c amd,radv,radeonsi: add ac_cmdbuf_flush_vgt_streamout()
Some checks are pending
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37870>
2025-10-16 06:31:41 +00:00
Samuel Pitoiset
679332f9a9 amd,radv,radeonsi: add ac_emit_cp_acquire_mem()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37870>
2025-10-16 06:31:40 +00:00
Samuel Pitoiset
9ad7fb8569 amd,radv,radeonsi: add ac_emit_cp_gfx_scratch()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37870>
2025-10-16 06:31:40 +00:00
Samuel Pitoiset
9ff8e71b4e amd,radv,radeonsi: add ac_emit_cp_tess_rings()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37870>
2025-10-16 06:31:39 +00:00
Samuel Pitoiset
47a64f5b6f amd,radv,radeonsi: add ac_emit_cp_gfx11_ge_rings()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37870>
2025-10-16 06:31:38 +00:00
Samuel Pitoiset
044bafb6ac amd: add a predicate parameter to ac_emit_cp_pfp_sync_me()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37870>
2025-10-16 06:31:36 +00:00
Samuel Pitoiset
48b4a43e8f amd,radv,radeonsi: add ac_emit_cp_set_predication()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37870>
2025-10-16 06:31:36 +00:00
Samuel Pitoiset
426d48d41e radeonsi: use ac_emit_write_data_imm() more
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37870>
2025-10-16 06:31:34 +00:00
Faith Ekstrand
1fbc73836e intel: Drop intel_mem.c/h
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37803>
2025-10-16 01:19:45 +00:00
Faith Ekstrand
f4a4c95d0c crocus: Use util_flush_inval_range()
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37803>
2025-10-16 01:19:45 +00:00