Commit graph

102109 commits

Author SHA1 Message Date
Jason Ekstrand
14e0a222d9 spirv: Use the LOCAL_GROUP_SIZE system value
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-04-09 19:45:25 -07:00
Jason Ekstrand
131d454c35 nir/lower_system_values: Support SYSTEM_VALUE_LOCAL_GROUP_SIZE
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-04-09 19:45:25 -07:00
Lionel Landwerlin
f3353e53db intel: aubinator: print out addresses of invalid instructions
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2018-04-10 00:58:38 +01:00
Bas Nieuwenhuizen
41fbcc7901 radv: Always reset draw user SGPRs after secondary command buffer.
As we sometimes reset them to -1, -1 does not mean that they are
not written by the secondary command buffer.

Fixes: ad11fc3571 "radv: don't emit unneeded vertex state."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-04-09 23:04:42 +02:00
Bas Nieuwenhuizen
74b0b869dd radv: Don't set instance count using predication.
The packet can sometimes be skipped, but we still think the change takes effect.

This just makes the packet always take effect.

Fixes: ad11fc3571 "radv: don't emit unneeded vertex state."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105942
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-04-09 23:04:35 +02:00
Rob Clark
d66dc34316 mesa/st/nir: fix instruction removal
At one point this kinda worked (or at least didn't cause problems).  But
with deref-instructions it results in dangling deref instructions not
being properly removed.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-09 15:36:21 -04:00
Rob Clark
becf2d1fac mesa/st/nir: fix naked lowering pass call
Not using the macro means no nir_validate in debug builds, resulting in
problems showing up only after later passes.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-09 15:36:21 -04:00
Rob Clark
c4457113e9 nir: add comment about nir_src_copy()
So it is more clear about when to use nir_instr_rewrite_src()

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-09 15:36:21 -04:00
Nanley Chery
1d94aa1987 i965: Make the miptree clear color setter take a gl_color_union
We want to hide the internal details of how the miptree's clear color
is calculated.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-09 10:56:48 -07:00
Nanley Chery
3dbb49a978 i965/miptree: Move the clear color and value setter implementations
These will get more complex in later commits.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-09 10:56:48 -07:00
Nanley Chery
1ce7ae391e i965: Use the brw_context for the clear color and value setters
Do what all the other functions in the miptree API do.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-09 10:56:48 -07:00
Bas Vermeulen
c63bef15fc radeonsi: convert dispatch packet to little endian
The parameters for the compute engine are wrong when using
an E8860 on a big endian machine.
To fix this, convert the contents of struct dispatch_packet
to little endian.

This ensures that get_global_id(0) and similar functions
in the OpenCL code get the correct endian values, and
makes my simple OpenCL program work correctly.

Signed-off-by: Bas Vermeulen <bas@daedalean.ai>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2018-04-09 13:47:52 -04:00
Bas Vermeulen
be628e4749 radeonsi: correct si_vgt_param_key on big endian machines
Using mesa OpenCL failed on a big endian PowerPC machine because
si_vgt_param_key is using bitfields and a 32 bit int for an
index into an array.

Fix si_vgt_param_key to work correctly on both little endian
and big endian machines.

Signed-off-by: Bas Vermeulen <bas@daedalean.ai>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-04-09 13:42:30 -04:00
Marek Olšák
f33e4482b3 radeonsi: don't set RB+ registers on GFX9 chips without RB+
CLEAR_STATE initializes them properly.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-04-09 13:40:25 -04:00
Emil Velikov
ea2536cd26 etnaviv: meson: add etnaviv_query_pm.[ch] to the sources
Otherwise building the driver will fail with unresolved symbols.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105960
Fixes: 72d2043be0 ("etnaviv: add perfmon query implementation")
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Clayton Craft <clayton.a.craft@intel.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-04-09 19:09:24 +02:00
Xiong, James
f23b45dce3 i965: return the fourcc saved in __DRIimage when possible
When creating a image from a texture, the image's dri_format is
set to the first plane's format, and used to look up for the
fourcc. e.g. for FOURCC_NV12 texture, the dri_format is set to
__DRI_IMAGE_FORMAT_R8, we end up with a wrong entry in function
intel_lookup_fourcc():
   { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1,
     { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
instead of the correct one:
   { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
     { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
       { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },
as a result, a wrong fourcc __DRI_IMAGE_FOURCC_R8 was returned.

To fix this bug, the image inherits the texture's planar_format that
has the original fourcc; Upon querying, if planar_format is set,
return the saved fourcc; Otherwise fall back to the old way.

v3: add a bug description and "cc mesa-stable" tag (Jason)
  remove redundant null pointer check (Tapani)
  squash 2 patches into one (James)
v2: fall back to intel_lookup_fourcc() when planar_format is NULL
  (Dongwon & Matt Roper)

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Xiong, James <james.xiong@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-04-09 18:16:59 +03:00
Bastien Orivel
42c2f5b579 nir: Fix a typo in src/compiler/Makefile.nir.am
Since 31d91f019b, the makefile tries to
find the file SConstript.spirv instead of SConscript.spirv which breaks
the make dist command.

Reviewed-by: Brian Paul <brianp@vmware.com>
2018-04-09 08:32:45 -06:00
Samuel Pitoiset
04e609f1f8 radv: fix prefetching of vertex shader and VBOs on SI
Forgot one check... Too many mistakes for a simple change.

Fixes: f1d7c16e85 ("radv: fix prefetching compute shaders on CIK and older chips")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 16:14:12 +02:00
Samuel Pitoiset
56a4d03b0c radv: implement VK_AMD_shader_core_properties
Simple extension that only returns information for AMD hw.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 14:28:13 +02:00
Samuel Pitoiset
466aba9fa2 radv: add RADV_NUM_PHYSICAL_VGPRS constant
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 14:28:13 +02:00
Samuel Pitoiset
2f7bb93146 radv: add radv_get_num_physical_sgprs() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 14:28:13 +02:00
Samuel Pitoiset
b30dec738a vulkan: Update the XML and headers to 1.1.72
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 14:28:13 +02:00
Andres Gomez
a055f5108d docs: properly escape characters
Signed-off-by: Andres Gomez <agomez@igalia.com>
2018-04-09 13:47:40 +03:00
Andres Gomez
7cf3932098 mesa: adds some comments regarding MESA_GLES_VERSION_OVERRIDE usage
Fixes: 03fd6704db ("mesa: Add support for a new override string
MESA_GLES_VERSION_OVERRIDE")

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-04-09 13:47:40 +03:00
Marek Olšák
806ab42c0f mesa: simplify MESA_GL_VERSION_OVERRIDE behavior of API override
v2:
 - Provide a correct explanation on the envvars documentation (Ian).
 - Provide a more correct explanation on the function comments (Andres).
v3:
 - Homogenize documentation and inline comments (Emil).
 - Correct a typo (Emil).

Fixes: 2599b92eb9 ("mesa: allow forcing >=3.1 compatibility contexts
with MESA_GL_VERSION_OVERRIDE")

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ian Romanick <ian.d.romanick@intel.com>
Cc: Eric Engestrom <eric.engestrom@imgtec.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-04-09 13:47:40 +03:00
Andres Gomez
c6067fcd07 dri_util: don't fail when not supporting ARB_compatibility with GL3.1
Currently, any driver that does not support the ARB_compatibility
extension will fail on GL3.1 context creation if the application does
not request the forward-compatiblity flag.

Restore the original check which changes mesa_api to API_OPENGL_CORE,
only when:
 - GL3.1 is requested, without the forward-compatiblity flag.
 - driver does not support ARB_compatibility - as deduced by
max_gl_compat_version.

Fixes: a0c8b49284 ("mesa: enable OpenGL 3.1 with ARB_compatibility")

v2:
 - Improve commit log (Emil).
 - Provide a correct explanation on the features documentation (Ian).

Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Ian Romanick <ian.d.romanick@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Eric Engestrom <eric.engestrom@imgtec.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-04-09 13:46:34 +03:00
Andres Gomez
044acd3569 dri_util: when overriding, always reset the core version
This way we won't fail when validating just because we may have a non
overriden core version that is lower than the requested one, even when
the compat version is high enough.

For example, running glcts from VK-GL-CTS with i965, this will
succeed:

$ MESA_GL_VERSION_OVERRIDE=4.6 ./glcts --deqp-case=KHR-GL46.info.vendor

While, this will fail:

$ MESA_GL_VERSION_OVERRIDE=4.6COMPAT ./glcts --deqp-case=KHR-GL46.info.vendor

Fixes: 464c56d3d5 ("dri_util: Use
_mesa_override_gl_version_contextless")

Cc: Ian Romanick <ian.d.romanick@intel.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-04-09 13:18:16 +03:00
Samuel Pitoiset
b0f8ad189c radv: add radv_image_is_tc_compat_htile() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 11:21:26 +02:00
Samuel Pitoiset
95d5ad80e9 radv: add radv_use_dcc_for_image() helper
And add some TODOs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 11:21:24 +02:00
Samuel Pitoiset
fab5fe4284 radv: rename radv_image_is_tc_compat_htile()
... to radv_use_tc_compat_htile_for_image(). This function
name makes more sense to me because we want to know if and
only if TC-compat HTILE should be used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 11:21:21 +02:00
Samuel Pitoiset
2692736cee radv: simplify a check in radv_initialise_color_surface()
If the image has FMASK metadata, the number of samples is > 1
because radv_image_can_enable_fmask() handles that already.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 11:21:16 +02:00
Samuel Pitoiset
ed41e776d0 radv: clean up radv_vi_dcc_enabled()
And rename to radv_dcc_enabled() to be consistent.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 11:21:14 +02:00
Samuel Pitoiset
e213f19907 radv: clean up radv_htile_enabled()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 11:21:12 +02:00
Samuel Pitoiset
0fc9113ac5 radv: add radv_image_has_{cmask,fmask,dcc,htile}() helpers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 11:21:10 +02:00
Samuel Pitoiset
32f5174ce8 radv: add radv_get_cmask_fast_clear_value() helper
DCC for MSAA textures are currently unsupported but that will
be used later on.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 11:21:08 +02:00
Samuel Pitoiset
f882c62218 radv: add radv_clear_{cmask,dcc} helpers
They will help for DCC MSAA textures and if we support mipmaps
in the future.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-09 11:21:05 +02:00
Axel Davy
d899826733 st/nine: Do not use scratch for face register
Scratch registers are reused every instructions.
Since vFace is reused, a new temporary register
should be used.

Fixes: https://github.com/iXit/Mesa-3D/issues/311

Signed-off-by: Axel Davy <davyaxel0@gmail.com>

CC: "17.3 18.0" <mesa-stable@lists.freedesktop.org>
2018-04-08 22:49:43 +02:00
Christian Gmeiner
9e80273693 etnaviv: expose perfmon query groups
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
2018-04-08 22:23:45 +02:00
Christian Gmeiner
c320b158f5 etnaviv: add query_group_info for perfmon counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
2018-04-08 22:23:38 +02:00
Christian Gmeiner
5a3b744ed2 etnaviv: assign group_ids to perfmon queries
Prep work for AMD_performance_monitor support.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
2018-04-08 22:23:34 +02:00
Christian Gmeiner
4020fa3e08 etnaviv: support MC performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
2018-04-08 22:21:40 +02:00
Christian Gmeiner
3c3f936ae1 etnaviv: support TX performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
2018-04-08 22:21:12 +02:00
Christian Gmeiner
f380ce13f0 etnaviv: support RA performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
2018-04-08 22:21:04 +02:00
Christian Gmeiner
3af0e228e5 etnaviv: support SE performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
2018-04-08 22:20:50 +02:00
Christian Gmeiner
9ae86c1306 etnaviv: support PA performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
2018-04-08 22:20:46 +02:00
Christian Gmeiner
69bebe06e3 etnaviv: support SH performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
2018-04-08 22:20:42 +02:00
Christian Gmeiner
1f603402f6 etnaviv: support PE performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
2018-04-08 22:20:37 +02:00
Christian Gmeiner
d0bed0b494 etnaviv: support HI performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
2018-04-08 22:20:32 +02:00
Christian Gmeiner
72d2043be0 etnaviv: add perfmon query implementation
Add needed infrastructure to use performance monitor
requests for queries.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
2018-04-08 22:20:25 +02:00
Christian Gmeiner
7e3dba301e etnaviv: sw queries: return correct number of groups
Fixes: 3d912bd742 ("etnaviv: add query_group_info for sw counters")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-04-08 22:13:04 +02:00