4 commits

Author	SHA1	Message	Date
Qiang Yu	1461b5f61b	nir: add image fragment mask load intrinsic ... Like nir_texop_fragment_mask_fetch_amd, this is used to load multi sample image fmask data for AMD GPU. We will lower multi sample image load and samples_identical intrinsics to use it latter for radeonsi. RADV does not need this because it always expand fmask images before dispatch compute shader. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18666>	2022-12-19 09:22:11 +08:00
Marek Olšák	ea6993f9c7	nir: add nir_intrinsic_image_samples_identical ... radeonsi will use it Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17693>	2022-08-03 17:44:15 +00:00
Marek Olšák	f7a77ff900	nir: fix an uninitialized variable valgrind warning in nir_group_loads ... pass_flags is only initialized for grouped loads, so change the order Fixes: 33b4eb149e - nir: add new SSA instruction scheduler grouping loads into indirection groups Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16090>	2022-04-22 18:18:09 +00:00
Marek Olšák	33b4eb149e	nir: add new SSA instruction scheduler grouping loads into indirection groups ... Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13604>	2021-11-08 21:20:11 +00:00