Commit graph

27608 commits

Author SHA1 Message Date
Marek Olšák
ed95cb3a31 radeonsi: add checks for a NULL pixel shader
This will allow removing the dummy PS.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-24 00:01:20 +02:00
Marek Olšák
d842d2f251 gallium/util: add a test for NULL fragment shaders
Just to validate that radeonsi doesn't crash.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-24 00:01:20 +02:00
Samuel Li
bf0d0ce0d5 radeonsi: add support for Stoney asics (v3)
v2 (agd): rebase on mesa master, split pci ids to
separate commit
v3 (agd): use carrizo for llvm processor name for
llvm 3.7 and older

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Samuel Li <samuel.li@amd.com>
Cc: mesa-stable@lists.freedesktop.org
2015-10-23 17:53:14 -04:00
Ilia Mirkin
e05021ff72 nvc0: respect edgeflag attribute width
The edgeflag comes in as ubyte with glEdgeFlagPointer but as float with
plain immediate glEdgeFlag. Avoid reading bytes that weren't meant for
the edgeflag in the pointer case.

Fixes intermittent failures with gl-2.0-edgeflag piglit (and valgrind
complaints about reading uninitialized memory).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2015-10-23 16:43:06 -04:00
Jose Fonseca
ea421e919a gallivm: Explicitly disable unsupported CPU features.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92214
CC: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-10-23 20:25:19 +01:00
Eric Anholt
70b06fb5d5 vc4: Convert blending to being done in 4x8 unorm normally.
We can't do this all the time, because you want blending to be done in
linear space, and sRGB would lose too much precision being done in 4x8.
The win on instructions is pretty huge when you can, though.

total uniforms in shared programs: 32065 -> 32168 (0.32%)
uniforms in affected programs:     327 -> 430 (31.50%)
total instructions in shared programs: 92644 -> 89830 (-3.04%)
instructions in affected programs:     15580 -> 12766 (-18.06%)

Improves openarena performance at 1920x1080 from 10.7fps to 11.2fps.
2015-10-23 18:11:21 +01:00
Eric Anholt
8e701fda49 vc4: Add QIR/QPU support for the 8-bit vector instructions. 2015-10-23 18:11:21 +01:00
Eric Anholt
817a7eb588 vc4: Don't try to CSE non-SSA instructions.
This can happen when we're doing destination packing -- we don't know
what's in the rest of the register.

Signed-off-by: Eric Anholt <eric@anholt.net>
2015-10-23 18:11:21 +01:00
Eric Anholt
1066a372d8 vc4: Add dumping of VC4_PACKET_GL_INDEXED_PRIMITIVE. 2015-10-23 18:11:21 +01:00
Eric Anholt
7d7fbcdf4e vc4: Add a workaround for HW-2116 (state counter wrap fails).
I haven't proven that this happens (I've got other GPU hangs in the
way), but the closed driver also does this and it's documented as an
errata.
2015-10-23 18:11:21 +01:00
Eric Anholt
73f6104532 vc4: Fix missing \n in a perf_debug(). 2015-10-23 18:11:21 +01:00
Eric Anholt
fb064901e9 vc4: Use Rob's NIR-based user clip lowering. 2015-10-23 14:30:15 +01:00
Eric Anholt
b3797a8f88 vc4: Also dump the decimation mode for resolved stores. 2015-10-23 14:30:15 +01:00
Eric Anholt
7516cbd261 vc4: Use VC4_GET_FIELD and other defines in dumping VC4_RENDER_CONFIG. 2015-10-23 14:30:15 +01:00
Eric Anholt
b0963ce758 vc4: Add a sentinel after simulator buffers for buffer overflow detection.
This is a little bit like the mprotect-based fencing I've experimented
with, but it's simple and low overhead.  The downside is that only catches
writes, not reads.

It didn't catch any bad writes on a current piglit run, but may be useful
in the future.
2015-10-23 14:29:07 +01:00
Chia-I Wu
582ecb3b91 ilo: add support for scratch spaces
When a kernel reports a non-zero per-thread scratch space size, make sure the
hardware state is correctly set up, and a scratch bo is allocated.
2015-10-23 17:29:58 +08:00
Chia-I Wu
4a7d18296a ilo: fix scratch space setup in core
Move scratch_size out of ilo_state_shader_kernel_info and
ilo_state_compute_interface_info.  A scratch space is shared by all
kernels/interfaces.  Update builder to emit relocs for scratch bos.
2015-10-23 17:29:58 +08:00
Dave Airlie
b3b82fe8ea virgl/vtest: add vtest driver
virgl/vtest is a swrast driver that allows the
virgl acceleration to be tested without having
a virtual machine.

The backend has a unix socket server that
this connects to.

This is run by setting
LIBGL_ALWAYS_SOFTWARE=y
GALLIUM_DRIVER=virpipe

In this mode all renderering is sent over
a socket to the remote renderer, and the
results are readback and copies to the screen
using drisw. This works well enough to develop
new features and to help debug.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-10-23 14:40:07 +10:00
Dave Airlie
a8987b88ff virgl: add driver for virtio-gpu 3D (v2)
virgl is the 3D acceleration backend for the
virtio-gpu shipping with qemu.

The 3D acceleration is designed around gallium
and TGSI as the virtualisation layer. The backend
renderer translates the virgl interface into
OpenGL currently.

This is the initial import of the driver to mesa.

The kernel driver portions are lined up for drm-next.

Currently this driver supports up to GL3.3 and some
misc extensions if the host driver exposes it. It is
planned to iterate the virgl API to new GL levels
as mesa host drivers gain features.

v2: fix resource tracking across flushes to avoid
->bind hack in mapping.
consolidate mapping and waiting code for transfers.
use u_range for dirt tracking.
handle larger shaders in protocol.
include virtgpu_drm.h in mesa for now.
add translation layer for gallium tgsi to virgl tgsi.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-10-23 14:40:07 +10:00
Dave Airlie
531f5d1270 tgsi: try and handle overflowing shaders. (v2)
This is used to detect error in virgl if we overflow the shader
dumping buffers.

v2: return a bool.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-10-23 11:57:56 +10:00
Dave Airlie
041081dc21 tgsi: add option to dump floats as hex values
This adds support to the parser to accept hex values as floats,
and then adds support to the dumper to allow the user to select
to dump float as 32-bit hex numbers.

This is required to get accurate values for virgl use of TGSI.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-10-23 11:55:02 +10:00
Sinclair Yeh
231d539239 svga: Condition preemptive flush on draw emission
On ultra high resolution modes, the preemptive flush flag can be
set midway through command submission, a condition that cannot be
recovered from a flush-retry, causing rendering artifacts.

This patch prevents a preemtive_flush until a draw has been
emitted.

Signed-off-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2015-10-22 17:19:20 -06:00
Brian Paul
99effaa965 svga: try to avoid index generation for some primitive types
The svga device doesn't directly support quads, quad strips or polygons
so we have to convert those types to indexed triangle lists.  But we
can sometimes avoid that if we're drawing flat/constant-colored prims
and we don't have to worry about provoking vertex.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2015-10-22 17:19:20 -06:00
Brian Paul
129d34da49 svga: avoid provoking vertex conversion when possible
Provoking vertex comes into play when doing flat shading.  But if we know
that all fragments in a primitive are the same color, the provoking vertex
doesn't matter.  Check for that case and use whichever provoking vertex
convention is supported by the device.

This avoids generating an index buffer to do the PV conversion.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2015-10-22 17:19:20 -06:00
Brian Paul
1082735bb6 svga: detect constant color writes in fragment shaders
Examine the fragment shader to try to detect TGSI shaders which use
"MOV OUT[0], CONST[i]" to write a constant value for the fragment color.
In this case, all fragments will have the same color (unless blending is
enabled).

This is a common case for OpenGL code such as: glColor(), glBegin(),
glVertex(), ..., glEnd() when lighting/fog/etc are disabled.  In this
case, the Mesa/gallium state tracker actually generates a simple
"MOV OUT[0], CONST[i]" fragment shader.

This will be used by the next commit to avoid provoking vertex conversion
(creating/rewriting an index buffer) when drawing flat-shaded primitives.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2015-10-22 17:19:20 -06:00
Alex Deucher
7b63658125 radeon/uvd: don't expose HEVC on old UVD hw (v3)
The section for UVD 2 and older was not updated
when HEVC support was added. Reported by Kano
on irc.

v2: integrate the UVD2 and older checks into the
main switch statement.
v3: handle encode checking as well.  Encode is
already checked in the top case statement, so
drop encode checks in the lower case statement.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
2015-10-22 16:22:44 -04:00
Jose Fonseca
718249843b gallivm: Translate all util_cpu_caps bits to LLVM attributes.
This should prevent disparity between features Mesa and LLVM
believe are supported by the CPU.

http://lists.freedesktop.org/archives/mesa-dev/2015-October/thread.html#96990

Tested on a i7-3720QM w/ LLVM 3.3 and 3.6.

v2: Increase SmallVector initial size as suggested by Gustaw Smolarczyk.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
CC: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
2015-10-22 11:11:40 +01:00
Chia-I Wu
13a5805b64 ilo: make sure there is HiZ before resolving
We do not want to perform a depth resolve on an MCS enabled surface.
2015-10-22 14:06:21 +08:00
Chia-I Wu
0b6f6ee50f ilo: fix max thread count for HS on Gen8
It is in DW2 on Gen8.
2015-10-22 14:06:21 +08:00
Brian Paul
18a631eb90 svga: fix clip plane regression after recent tgsi_scan change
Before the change "tgsi/scan: use properties for clip/cull distance
writemasks", the tgsi_shader_info::num_written_clipdistance field
was a multiple of four, now it's an accurate count.  In the svga
driver, we need a minor change to the loop test.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2015-10-21 17:12:19 -06:00
Nigel Stewart
04703762e5 osmesa: Expose GL entry points for Windows build via DEF file.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92437
CC: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jose Fonseca <jfonseca@vmware.com>
2015-10-21 14:06:58 +01:00
Brian Paul
f1682fdafa svga: add switch case for PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
A third instance of this was needed but missed in the previous commit.
Return 32 as for the two other cases.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2015-10-20 19:14:51 -06:00
Brian Paul
b48e16fa2f draw: fix splitting of line loops (v2)
When the draw module splits long line loops, the sections are emitted
as line strips.  But the primitive type wasn't set correctly so each
section was being drawn as a loop, introducing extra line segments.

To fix this, we pass a new DRAW_LINE_LOOP_AS_STRIP flag to the run()
function.  The linear/elt_run() functions have to check for this flag
and set their primitive type accordingly.

No piglit regressions.  Fixes piglit's lineloop with -count 4097 or
higher.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81174

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-10-20 19:14:51 -06:00
Marek Olšák
814f31457e gallium: add PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
This avoids a serious r600g bug leading to a GPU hang.
The chances this bug will get fixed are pretty low now.

I deeply regret listening to others and not pushing this patch, leaving
other users with a GPU-crashing driver. Yes, it should be fixed
in the compiler and it's ugly, but users couldn't care less about that.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86720

Cc: 11.0 10.6 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2015-10-20 18:27:11 +02:00
Eric Anholt
921feb8782 vc4: Switch our vertex attr lowering to being NIR-based.
This exposes more information to NIR's optimization, and should be
particularly useful when we do range-based optimization.

total uniforms in shared programs: 32066 -> 32065 (-0.00%)
uniforms in affected programs:     21 -> 20 (-4.76%)
total instructions in shared programs: 93104 -> 92630 (-0.51%)
instructions in affected programs:     31901 -> 31427 (-1.49%)
2015-10-20 12:47:27 +01:00
Eric Anholt
85b946478c vc4: Add limited support for ibfe/ubfe.
This is just enough to cover our unpack modes, which will be used by some
new NIR-based lowering in the next commit.
2015-10-20 12:47:27 +01:00
Marek Olšák
8910ebd8e8 tgsi/scan: use properties for clip/cull distance writemasks
No changes needed for drivers already relying on tgsi_shader_info.

Reviewed-by: Brian Paul <brianp@vmware.com>
2015-10-20 12:58:25 +02:00
Marek Olšák
e70c66197e gallium: add new properties for clip and cull distance usage
The TGSI usage mask can't be used, because these are declared as an output
array of 2 elements.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
2015-10-20 12:58:25 +02:00
Marek Olšák
8339585b12 radeonsi: enable BC_OPTIMIZE if centroid isn't used
This solution was recommended by a Catalyst developer.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-20 12:56:46 +02:00
Marek Olšák
38391835b5 radeonsi: fix the export_prim_id field size in the shader key
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-20 12:56:40 +02:00
Marek Olšák
9b54ce3362 radeonsi: support thread-safe shaders shared by multiple contexts
The "current" shader pointer is moved from the CSO to the context, so that
the CSO is mostly immutable.

The only drawback is that the "current" pointer isn't saved when unbinding
a shader and it must be looked up when the shader is bound again.

This is also a prerequisite for multithreaded shader compilation.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-20 12:51:51 +02:00
Marek Olšák
d74e7b6fb9 gallium: add PIPE_CAP_SHAREABLE_SHADERS
I'll let drivers figure out how to do it.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-10-20 12:51:51 +02:00
Marek Olšák
12321966ae radeonsi: add support for ARB_texture_view
All tests pass. We don't need to do much - just set CUBE if the view
target is CUBE or CUBE_ARRAY, otherwise set the resource target.

The reason this can be so simple is that texture instructions
have a greater effect on the target than the sampler view.

Thanks Glenn for the piglit test.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-20 12:25:19 +02:00
Boyan Ding
6bd9e03512 vc4: Use nir_foreach_variable
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2015-10-20 09:54:53 +01:00
Leo Liu
867284a8f0 st/omx/dec/h264: fix field picture type 0 poc disorder
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
2015-10-19 20:43:03 -04:00
Jose Fonseca
b23a4859f4 scons: Build nir/glsl_types.cpp once.
Undoes early hacks, and ensures nir/glsl_types.cpp is built once, and
only once.

The root problem is that SCons doesn't know about NIR nor any source
file in the NIR_FILES source list.

Tested with libgl-gdi and libgl-xlib scons targets.

Reviewed-by: Brian Paul <brianp@vmware.com>
2015-10-19 15:59:59 +01:00
Brian Paul
530eb39c71 svga: fix incorrect round-down arithmetic
Spotted by Roland.  Luckily, this code should never really be hit
since the const buffer size and offset should already be multiples
of 16.  I could probably add more assertions to that effect, but
let's just fix the arithmetic for now.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-10-19 08:54:42 -06:00
Indrajit Das
b0a44f1017 st/va: Added support for NV12 to IYUV conversion in vlVaGetImage
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-10-19 09:47:33 +02:00
Indrajit Das
381c17d695 st/va: Used correct parameter to derive the value of the "h" variable in vlVaCreateImage
Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-10-19 09:47:24 +02:00
Chia-I Wu
86ccb2a16f ilo: set VME for 3DSTATE_PS
When the bit is not set, we can see sampling artifacts on triangle edges when
the mip filter is not GEN6_MIPFILTER_NONE.
2015-10-18 21:35:16 +08:00