Both Panfrost and Panthor are expected to implement these in a
device-specific way.
Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34224>
Without it, BGR8 gets a NULL entry, and it trips out the GPU when it
gets passed a blend descriptor with RGB8 as a format to convert to.
Fixes: bba4785f60 ("pan/format: Add render target support for R8G8B8/B8G8R8 formats")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35715>
Add render target support to the existing R8G8B8/B8G8R8 formats
and add the B8G8R8_UNORM format.
Signed-off-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34889>
This ensures proper behaviors of pan_compute_npot_divisor by using the
same algorithm as the hardware to perform the division.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35490>
It's not that magical those days.
This also give proper names around the codebase for exponent and
epsilon.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35490>
We are going to need those functions in indirect CL codepaths.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35490>
We are going to move everything in pan_encode.h for CL usage.
This inline the code used by pan_padded_vertex_count.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35490>
It was based on reverse engineering and inaccurate.
This also get ride of fp64 usage and will allow us to use it in OpenCL C
shaders for indirect/indexed draw.
On the full 32-bit range, this fixes ~10 millions inaccurate results.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: 467ae0d39d ("panfrost: Factor out panfrost_compute_magic_divisor")
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35490>
8x and 16x MSAA should work now, so we no longer need to deal with those
separately. We have more accurate checks for when it's supported or not
in place already.
2x MSAA isn't supported at all until v12, which we haven't finished
wiring up yet. So let's leave that one for now... We'll need some more
fixes for that anyway.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34455>
We recently found a weird case where an image was re-interpreted with
a format that had a bigger size than the image format, which led the
resulting texture descriptor to have a size that was bigger than what
the plane descriptors were covering.
Let's make sure this sort of unexpected use don't slip through in the
future by introducing basic image view consistency checks.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35317>
Adds support for reading PrimitiveID in a fragment shader assuming the
previous shader was vertex.
If support for shaders that can modify PrimitiveID is added, additional
changes will be required.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35367>
Now that we use a precomp shader for indirect dispatch,
we can safely remove this.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32839>
Will be used for indirect dispatch.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32839>
This change and the prior preparations have fixed the false assumption
of ordered image planes for external multi-planar image (YV12 has the
chroma planes swapped to map to the Vulkan format). We no longer need to
use plane data size to advance plane offset. The code paths for
subresource reporting, memroy reporting and memory binding are now
consistent across native disjoint/non-disjoint and imported external
images no matter single-planar or multi-planar.
Test:
- No regressions in dEQP-VK.ycbcr.*
- NV12 camera preview works on Android
- YV12 video playback works on Android
- Android graphics cts passing
- BasicVulkanGpuTest
- MediaVulkanGpuTest
- CameraVulkanGpuTest
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35299>
This change:
1. Rename pan_image_wsi_layout to pan_image_layout_constraints.
1. Document that pan_image_layout_constraints::offset_B will be used to
pass planar plane offset for native images as well. Update
array_stride_B to exclude such offset accordingly.
2. Document that whether explicit layout is used further depends on if
the passed wsi_row_pitch_B is non-zero or not. Updated the checks to
base on the new boolean use_explicit_layout.
3. Update and document the intended slice offset_B behavior so that
native and imported images are aligned.
No behavior change from this commit since the client (panvk) hasn't set
the pan_image_layout_constraints->offset_B for planar plane yet.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35299>
This change splits pan_image_layout_get_wsi_layout into separate queries
to prepare for making pan_image_wsi_layout an input layout constraint.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35299>
This doesn't affect gallium side behavior since data_size_B is never
looked at for imported planar plane. For panvk, it doesn't affect
imported single planar image, and multi-planar side is still broken.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35299>
Putting compiler optimization aside, this at least improves readability
by making it clean which vars are mutable and which are immutable.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35299>
Extend the existing helpers to report the correct values when YUV formats
are involved.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
The way things are done at the moment, the pan_layout logic has no way
of knowing which plane is targeted, which either forces the user of
pan_image_layout_init() to patch the layout after the calculation based
on the YUV format.
These changes unblock unittests on YUV formats.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
So far we assumed tile rows would be tightly packed, so changing the
behavior without introducing a new set of AFBC modifiers is likely
to break some cases where the exported got the stride wrong. That's
still something we would like to enforce in the long run, so let's
start by adding a "PAN_MESA_DEBUG=strict_afbc" flag to exercise the
code supposed to force this behavior.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
Instead of picking random formats/extents, iterate over all supported
<format,modifier> for each architecture, and make sure
pan_image_layout_init() fails/suceeds when it's supposed to.
On success, we also make sure pan_image_layout_get_wsi_layout() returns
values that match the import.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
If we want to allow the import path to specify padding tiles, we need
to adjust pan_image_layout_get_wsi_layout() to base its WSI row pitch
calculation on the AFBC header row stride instead of the image width.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
At the moment, we check that the WSI pitch is big enough to cover the
resource width, but we don't validate that it's tile aligned, and we
also don't use the user provided pitch when AFBC is requested, meaning
we don't allow row tile padding.
Add an option to force using the explicit WSI pitch, and fail if the
pitch doesn't give a tile aligned row stride.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
If the offset is considered valid by wsi_row_pitch_to_row_stride() we
should use it as-is, even if it's suboptimal.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
We do a bunch of WSI -> GPU translation in there, so it makes sense to
also check that the offset and row stride are properly aligned, and
that the pixel width that results from this transformation is greater or
equal to the image width.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
We're not supposed to do AFBC(compressed), so there's no point testing
that in our AFBCFormatInvariant tests.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
This is not a valid combination.
Fixes: 2dae926850 ("panfrost: add utils for AFRC fixed-rate support")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
Not only the is_yuv() check in pan_afrc_get_format_info() didn't work,
because we use the multiplanar-RGB variants in panfrost, but we also
need the plane index to pick the right format.
Let's just assume AFRC(YUV) is not supported until someone decides to
add the necessary bits.
Fixes: 2dae926850 ("panfrost: add utils for AFRC fixed-rate support")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
pan_format_supports_afrc() returns true for formats that are then
rejected by pan_afrc_get_format_info(). Let's reconcile the two
helpers by using pan_afrc_get_format_info() to check for AFRC support.
Fixes: 894657a5ed ("panfrost: add support for AFRC modifiers")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
Will be used in pan_layout.c to validate the WSI info.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
Mali GPUs don't support DRM_FORMAT_MOD_MTK_16L_32S_TILE natively, so
it doesn't make sense to teach the common layer about this format,
especially since it would require adding more hacks to make sense of
the tiled -> linear view of such resources.
Given the only user of this format is the gallium driver, move the
MTK_TILED definitions there and start differentiating native and
emulated modifiers.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
We create hierarchy masks based on the number of levels available,
creating a bitmask with `max_levels` bits set. Originally these bits
all came together. Modify this to spread the bits out, which improves
performance on chips like the G31 with only 2 levels of hierarchy.
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34744>
These formats don't depend on the ASTC HDR texfeat, they depend on the
ASTC HDR texfeat. The ASTC HDR texfeat simply adds support for more
endpoint encodings to these formats.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35132>
Turns out, some Midgard GPUs don't support more than 4x MSAA. Add a
quirk for those GPUs, so don't expose it when it doesn't work.
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35184>
We can't easily pass multiple initializers here, because a comma in the
initializer list would be treated as a preprocessor argument separator
and not a separator in the initializer lst.
We could also have fixed this with some nested macro ugliness, but let's
instead do what nir_builder does for intrinsic indices and use __VA_ARGS__
to keep this neat.
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35184>
When using 16x MSAA, we have two sample-positions on the negative
boundary of the unit-square covering the pixel. This causes problems
when using the default tie-breaking rule, where we miss some
sample-positions when rasterizing primitives covering the entire
viewport.
This works fine on Bifrost and later, but this setting is ignored on
those GPUs, and they assume the default (e.g MINUS_180_OUT_0_IN).
Because we'd prefer for rasterization to match between Midgard and
Bifrost when we can, we only apply this when we have 16x MSAA.
As an added bonus, this behavior matches what the DDK does.
Fixes these tests when 16x MSAA is enabled:
- dEQP-GLES31.functional.texture.multisample.samples_16.use_texture_*
- dEQP-GLES3.functional.multisample.fbo_max_samples.proportionality_alpha_to_coverage
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35184>
The V4 GPUs doesn't have the dynamic allocation logic that V5 and later
has. There's nothing to calculate here; the GPU either supports 8x MSAA,
or 4x MSAA.
Since 8x MSAA is the architectural max, let's have this function report
that. We deal with the 4x limit separately as a quirk, because this
applies to some V5 GPUs as well.
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35184>
This value isn't valid on V4, so let's make sure we don't try to use it.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35184>
During direct dispatch, we calculate the size of the WLS allocation
based on the number of WLS instances which is an unbounded calculation
on number of workgroups.
This leads to extreme allocation sizes and potentially
VK_ERROR_OUT_OF_DEVICE_MEMORY for direct dispatches with a high amount
of workgroups.
This change adds an upper bound to the number of WLS instances, using
the same value we assume for indirect dispatches.
Additionally, this commit fixes the WLS max instance calculation (which
should be per core).
Fixes: 5544d39f44 ("panvk: Add a CSF backend for panvk_queue/cmd_buffer")
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: John Anthony <john.anthony@arm.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34979>
Specialize the texture emission logic for buffer views, which are much
simpler to deal with than image views.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34767>
Reflect the expected usage in the function name.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34767>
Split pan_image_layout into two pieces:
- pan_image_props containing all the properties set by the user of
pan_image_layout_init()
- pan_image_layout containing all the information constructed from
the image properties to describe the pixel layout
This allows us to clearly identify what's set by the user and what's
initialized from it. It will also allow us to share the image props
for multi-plane images.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34767>
Improve the layout code, based in part on the Asahi/Intel layout.
Suffixes like `_px` (for pixel), `_B` (for byte), `_el` (for element)
and `_sb` (for superblock) make some of the sizes of items within the
layout more explicit.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34767>
