this has a lot of caveats:
* extension must be supported
* resource must have usage bit set
* resource must not have any pending batch usage
* resource must be in supported layout
if all of these conditionals pass, then HIC can be used for direct image subdata
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Most drivers will want nir_opt_barrier_modes() to optimize out
unnecessary memory barrier modes. However, virgl has to translate
back to GLSL, which means it can really only handle partial memory
barriers in compute shaders today, because there isn't a proper
way to express them otherwise. Just ask nir_to_tgsi to promote
these back to full barriers as a workaround.
See KHR-GL43.shader_storage_buffer_object.advanced-readWrite-case1
on virpipe-on-gl as a case where this hack is needed.
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
this is the inverted version of rewrite_read_as_0 which tests for mismatched
component i/o on a given location and rewrites the inputs to zero if the
producer shader didn't write to the component
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Instead of failing the copy we can use multiple chunks.
This codepath shouldn't really be used since the source
image should usually be tiled but it still better to not
fail when possible.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24771>
previously non-separable progs had their libs owned exclusively by
the shaders, which meant it was possible for a background compile job
to crash while the context was being destroyed when accessing libs
which no longer had active shaders
fixes#9234
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25088>
In future patches, we will be creating a separate companion RCS engine
and each engine is created with it's own address space, and we really
don't want. CCS and RCS engine writes should be visible to each other in
order to get the wait/signal mechanism working.
v2:
- Move drm_i915_gem_context_create_ext_setparam out of if block (Lionel)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
The condition
!param->type->is_vector() || !param->type->is_scalar()
alawys evaluates to true:
* type is not scalar or vector -> true
* type is vector, i.e. num_components > 1 -> num_components == 1 is
false and !is_scalar() == true
* type is scalar, i.e. num_components == 1 -> num_components > 1 is
false and !is_vector() == true
There is no comment explaining why such code has been written, therefore
this seems to be a mistake.
To maintain consistency with the surrounding code,
glsl_type_is_scalar_or_vector has been used instead of
replacing || with &&.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24914>
Add fallback case to take into account driver reported tile restrictions if
default hardcoded tile configurations are not supported by driver
Reviewed-by: Tanner Van De Walle <tvandewalle@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25070>
Address loads that just load the index register don't need to chain
up like loads if the address register that are used for indirect
register loads. With the latter it is important that the load and the
address register use are in the same clause. For index register loads
this is scheduled accordingly.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24638>
The hardware is actually configures like this, but for fma64
we have to sacrifice a "normal" register to allocate z and w
channels, even though the result written there is not used.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24638>
Do explicit cast to suppress the below clang warnings,
../src/mesa/main/get.c:86:31: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
return ( ((F) * 65536.0f > INT_MAX) ? INT_MAX :
../src/mesa/main/texparam.c:967:27: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
((param > INT_MAX) ? INT_MAX : (GLint) (param + 0.5)) :
../src/mesa/main/texparam.c:2609:65: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
*params = LCLAMPF(obj->Sampler.Attrib.MinLod, INT_MIN, INT_MAX);
../src/mesa/main/texparam.c:2624:65: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
*params = LCLAMPF(obj->Sampler.Attrib.MaxLod, INT_MIN, INT_MAX);
../src/mesa/main/texparam.c:2648:72: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
*params = LCLAMPF(obj->Sampler.Attrib.MaxAnisotropy, INT_MIN, INT_MAX);
../src/mesa/main/texparam.c:2693:66: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
*params = LCLAMPF(obj->Sampler.Attrib.LodBias, INT_MIN, INT_MAX);
../src/gallium/drivers/freedreno/a3xx/fd3_emit.c:731:43: error: implicit conversion from 'unsigned int' to 'float' changes value from 4294967295 to 4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));
../src/gallium/drivers/freedreno/a3xx/fd3_emit.c:732:43: error: implicit conversion from 'unsigned int' to 'float' changes value from 4294967295 to 4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));
../src/nouveau/codegen/nv50_ir_peephole.cpp:1647:30: error: implicit conversion from 'unsigned int' to 'float' changes value from 4294967295 to 4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
CASE(TYPE_U32, u32, 0, UINT32_MAX, 0, INT32_MAX, 0, UINT32_MAX);
../src/nouveau/codegen/nv50_ir_peephole.cpp:1648:38: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
CASE(TYPE_S32, s32, INT32_MIN, INT32_MAX, INT32_MIN, INT32_MAX, 0, INT32_MAX);
../src/gallium/drivers/radeonsi/si_nir_lower_vs_inputs.c:400:51: error: implicit conversion from 'unsigned long long' to 'double' changes value from 18446744073709551615 to 18446744073709551616 [-Werror,-Wimplicit-const-int-float-conversion]
loads[chan] = nir_fmul_imm(b, tmp, 1.0 / BITFIELD64_MASK(bits));
../src/gallium/drivers/radeonsi/si_nir_lower_vs_inputs.c:408:43: error: implicit conversion from 'unsigned long long' to 'double' changes value from 18446744073709551615 to 18446744073709551616 [-Werror,-Wimplicit-const-int-float-conversion]
tmp = nir_fmul_imm(b, tmp, 1.0 / BITFIELD64_MASK(bits - 1));
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Acked-by: Helen Koike <helen.koike@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24362>
