Commit graph

195113 commits

Author SHA1 Message Date
Marek Olšák
ce72376641 radeonsi: rename SI_CONTEXT_* flags to SI_BARRIER_* flags
some of the definition names are changed completely

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
6f25ace87e radeonsi: add si_fb_barrier_before_rendering
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
0be3900b8d radeonsi: move DB synchronization into si_fb_barrier_after_rendering
Now these workarounds are applied everywhere.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
75d98f1db4 radeonsi: move CB synchronization into si_fb_barrier_after_rendering
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
dad0e0131b radeonsi: restructure fb_barrier code in si_launch_grid
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
895226e3ab radeonsi: move initial framebuffer barrier code into si_barrier.c
The new function si_fb_barrier_after_rendering will flag cache flushes and
waits in future commits. This is the beginning of unifying all framebuffer
barrier code.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
834aa812ea radeonsi: rename si_context::flags -> barrier_flags
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
ba53b57731 radeonsi: rewrite si_memory_barrier to generate fewer barrier flags
This is more optimal.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
03aec81290 radeonsi: check sctx->flags inside si_emit_barrier_direct
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
7cc2fee378 radeonsi: rename TC_L2_dirty -> L2_cache_dirty
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
0f063ed1e7 radeonsi: update remaining comments related to the L2 cache, use "L2", not "TC"
"GL2" is also OK. "TC-compatible" is also OK.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
311fafccef radeonsi: move most barrier code into a new file si_barrier.c
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
dac99e75af radeonsi: rename "cache_flush" -> "barrier"
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
214b4a119d radeonsi: remove unused buffer_subdata fallback from si_clear_buffer
It's never used.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
e1cfac91eb radeonsi: remove SI_CP_DMA_CLEAR_METHOD, call si_cp_dma_clear_buffer directly
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
47f6e05c6a radeonsi: replace SI_OP_CS_RENDER_COND_ENABLE with bool render_condition_enable
and the parameter is moved to the end in some cases, or second from the end.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
fc489d1855 radeonsi: enable conditional rendering for si_compute_shorten_ubyte_buffer
If the draw is conditional, the lowering should also be conditional.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
df6b5e3c05 radeonsi: remove unused flags and user_flags params from clear/copy functions
Remove the params from these:
- si_copy_buffer
- si_cp_dma_prepare
- si_cp_dma_clear_buffer
- si_cp_dma_realign_engine
- si_cp_dma_copy_buffer

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
2f4a9e65a7 radeonsi: change the flags parameter of si_compute_blit to bool fail_if_slow
That's the only flag we pass to it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
7432d2f19c radeonsi: remove SI_OP_SYNC_BEFORE* flags
We always pass SI_OP_SYNC_BEFORE to barriers, which makes it redundant.
If we don't want to sync "before", we just won't call
si_barrier_before_internal_op.

This makes the flags parameter unused in si_barrier_before_internal_op.
It might be used for something else in the future. All places now pass 0
to it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
0923bd1c5f radeonsi: remove unused SI_OP_IS_NESTED
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
c2d8cba0b4 radeonsi: always wait for idle before get_query_result_resource
The shader busy-waits until the query results are written, but that only
synchronizes for src. The destination buffer might also be used by previous
shaders, so we should wait until all shaders are idle. This might fix some
issues.

The missing si_mark_atom_dirty fix should have no effect, but all flags
changes should call it to be consistent.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
e8b474c921 radeonsi: always pass flags=0 into si_barrier_after_internal_op/simple_buffer_op
because the parameter is unused. It might be used differently in the future.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
eb6c098cd1 radeonsi: remove SI_OP_SYNC_AFTER
All places that call si_barrier_after_internal_op also set SI_OP_SYNC_AFTER,
so we can do the sync unconditionally.

If we want to skip the "after" sync in the future, we just won't call
si_barrier_after_internal_op.

CP DMA is the only one that will sync even without
si_barrier_after_internal_op, but CP DMA ops are usually small and almost
never used on GFX10+.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
d225fb3025 radeonsi: remove SI_OP_SKIP_CACHE_INV_BEFORE
The only remaining use had no effect because it doesn't call
si_barrier_before_internal_op at all and instead implements its own
barrier.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
67593f0c51 radeonsi: move barriers out of si_compute_shorten_ubyte_buffer
It turns out the barrier "before" didn't do anything.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
e805c35986 radeonsi: move barriers out of si_copy_buffer
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:58 +00:00
Marek Olšák
1ee394c34d radeonsi: move barriers out of si_clear_buffer
Some places need no barriers, while other places only need the barrier
after.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:57 +00:00
Marek Olšák
80a6f568e2 radeonsi: move barriers out of si_compute_clear_copy_buffer & si_cp_dma_*
Some places don't need si_barrier_before_simple_buffer_op.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:57 +00:00
Marek Olšák
5d607348a3 radeonsi: add barrier helpers for simple internal buffer ops
These just take dst and src parameters instead of lists of buffers and
images.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:57 +00:00
Marek Olšák
999b254ca8 radeonsi: remove unnecessary barriers from clear_buffer_rmw and clear_dcc_msaa
These didn't do anything because the caller implements its own barriers.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:57 +00:00
Marek Olšák
4194774edf radeonsi: move barriers out of si_launch_grid_internal_ssbos
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:57 +00:00
Marek Olšák
7d55f4d6d2 radeonsi: inline si_launch_grid_internal_images without the barriers
It has only one use. The barriers didn't do anything because the caller
doesn't set any flags and implements its own barrier.

This is part of trying to push the barrier logic outside the functions
that implement internal ops.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:57 +00:00
Marek Olšák
35727d2e9c radeonsi: remove SI_OP_CS_IMAGE
it's redundant now

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:57 +00:00
Marek Olšák
58d22e41af radeonsi: fix broken tessellation in Unigine Heaven
Test suites even with AMD_DEBUG=mono didn't catch this.

Fixes: b7136d0890 - radeonsi: pass TCS inputs_read mask to LS output lowering on GFX9 + monolithic

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
2024-09-17 20:44:57 +00:00
Georg Lehmann
a3d6a770c0 nir/instr_set: fix fp_fast_math
We can't just ignore the flags of the match, we need the union.

Fixes: 666647acae ("nir: track some float controls bits per instruction")

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31195>
2024-09-17 20:00:03 +00:00
Marek Olšák
0d8fe2d03b ac/nir/meta: tune clear/copy_buffer performance for gfx6-10.3
Finally, old GPUs have optimal clear/copy_buffer performance, but only
the top dGPU of each generation gets the best behavior.

Other dGPUs might need slightly different conditions.
APUs likely need very different conditions.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31082>
2024-09-17 15:19:32 -04:00
Marek Olšák
34bd8427f8 radeonsi/gfx12: fix shader uploads via CP DMA
It was incorrectly assumed that CP DMA is never used.

Fixes: c90d4e0d57 - radeonsi/gfx12: remove CP DMA workarounds because CP DMA is never used on gfx12

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31082>
2024-09-17 15:19:30 -04:00
Marek Olšák
e0f8993336 radeonsi: fix waiting for PS to finish if there are no CB/DB bindings on gfx6-8
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31082>
2024-09-17 15:19:26 -04:00
Pavel Ondračka
495e88eab5 r300: move HyperZ blacklist to driconf
Framework mostly copied from radeonsi...

The only change is the firefox override, which was not working anyway,
since firefox seems to no longer load mesa in the main process, so just
remove it.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30860>
2024-09-17 15:43:08 +00:00
David Rosca
009017c33c radeonsi: Disable EFC on VCN 2.2
VCN 2.2 doesn't support EFC.

Cc: mesa-stable

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31198>
2024-09-17 14:51:03 +00:00
Lionel Landwerlin
45377dc5c4 brw: fix vecN rebuilds
When loading a 64bit address from the push constants, we'll load a
vec2, so we need to allocate 2 GRFs and MOV each component.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11831
Fixes: 339630ab05 ("brw: enable A64 loads source rematerialization")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31010>
2024-09-17 14:22:23 +00:00
Lionel Landwerlin
c16b27f66f brw: use a builder of the size of the physical register for uniforms
Should avoid any partial write non-sense on Xe2+.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 339630ab05 ("brw: enable A64 loads source rematerialization")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31010>
2024-09-17 14:22:23 +00:00
Mike Blumenkrantz
31168bdbaa va/vl: add kopper support
requires LIBVA_DRIVER_NAME=zink

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30984>
2024-09-17 13:45:38 +00:00
Mike Blumenkrantz
55341689c8 vl/winsys: move dri3_get_screen_for_root to common
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30984>
2024-09-17 13:45:38 +00:00
Mike Blumenkrantz
3d79e51726 va: flush_resource before presentation
drivers require this to ensure presentation resources are present-able

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30984>
2024-09-17 13:45:38 +00:00
Boris Brezillon
b40ec57e36 panvk: Temporarily disable VK_FORMAT_D32_SFLOAT_S8_UINT on Valhall
Valhall doesn't support interleaved D32_S8X24 so let's not advertise
this format for now. Ultimately, we want to support it as a
multi-plane D32 + S8 format, and we probably want to switch Bifrost
to this layout too.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Tested-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Tested-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31165>
2024-09-17 13:13:58 +00:00
Boris Brezillon
7dc350ad76 pan/va: Accept DIM_SUBPASS[_MS] in valhall_tex_dimension()
We don't merge subpasses, so we can't turn subpass attachment
loads into tile buffer reads yet. Let's just treat those as
regular 2D textures for now (as we do on Bifrost).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11875
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Tested-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31166>
2024-09-17 12:51:27 +00:00
Lionel Landwerlin
0f6fa4679d clc: find opencl headers from the installed llvm/clang location
A number of people report the headers not being found when running
intel-clc. I've run into the same issue but only on the most recent
Ubuntu version.

Signed-off-by: Lionel Landwerlin <llandwerlin@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30711>
2024-09-17 14:29:19 +03:00
Tapani Pälli
0e02de5a50 iris: fix issues with memory object updates via glBufferSubData
Disable aysnc mapping in case we are updating a external memobj.

Fixes following Piglit tests:
   spec@ext_external_objects@vk-pix-buf-update-errors
   spec@ext_external_objects@vk-vert-buf-update-errors

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29303>
2024-09-17 10:06:58 +00:00