Commit graph

19225 commits

Author SHA1 Message Date
Rob Clark
1e6d290f21 freedreno: split out WFI helper
Mostly just to give an easy debug/instrumentation point.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-09-14 13:31:58 -04:00
Rob Clark
74052347f3 freedreno: fd_draw helper
Have a single helper that all draws come through.. mainly for a
convenient debug and instrumentation point.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-09-14 13:31:58 -04:00
Rob Clark
4712904ddc freedreno/a3xx: fix gpu lockup in some piglit tests
The varying-out config comes from the inputs of the frag shader (so that
we aren't exporting unneeded varyinges).  The varyings-count should come
from the frag shader as well, to avoid a discrepency in configuration
and resulting gpu lockup.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-09-14 13:31:58 -04:00
Rob Clark
64c134cedb freedreno/a3xx/compiler: add LIT
Needed by glxgears and etuxracer ;-)

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-09-14 13:31:58 -04:00
Rob Clark
cb9e07aa84 freedreno: multi-slice resources (cubemap, mipmap, etc)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-09-14 13:31:58 -04:00
Marek Olšák
f4e35f897e radeonsi: fix and enable transform feedback for CIK
The CP_STRMOUT_CNTL register was moved again.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-13 01:08:04 +02:00
Marek Olšák
f317ce5c5d radeonsi: fix gl_InstanceID with non-zero start_instance
start_instance doesn't affect gl_InstanceID.

There's no piglit test, but it's kinda obvious the code was wrong.

Reviewed-by: Christian König <christian.koenig@amd.com>
2013-09-13 01:08:03 +02:00
Marek Olšák
9c75d2f65b gallium: comment that INSTANCEID doesn't include start_instance
Reviewed-by: Christian König <christian.koenig@amd.com>
2013-09-13 01:08:03 +02:00
Marek Olšák
122a880b78 radeonsi: enable streamout AKA transform feedback for SI
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-13 01:07:56 +02:00
Marek Olšák
8d03d923b6 radeonsi: implement streamout shader support
The shader is responsible for writing to streamout buffers using
the TBUFFER_STORE_FORMAT_* instructions.

The locations of some input SGPRs and VGPRs are assigned dynamically, because
the input SGPRs controlling streamout are not declared if they are not needed,
decreasing the indices of all following inputs.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-13 01:04:44 +02:00
Marek Olšák
9d16e70b3f radeonsi: implement glDrawTransformFeedback functionality
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-13 01:04:44 +02:00
Marek Olšák
6cf29c7dab radeonsi: fix streamout queries
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-13 01:04:44 +02:00
Marek Olšák
91ede46222 radeonsi: implement streamout flush properly
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-13 01:04:44 +02:00
Marek Olšák
2993ccab38 radeonsi: bind streamout buffers to VGT and the vertex shader
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-13 01:04:44 +02:00
Marek Olšák
e4c5d3ee27 radeonsi: handle rasterizer_discard and set GS_OUT_PRIM_TYPE
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-13 01:04:44 +02:00
Marek Olšák
9eb3b9dc2b radeonsi: initialize the first CS like any other
So that the "init" state is always emitted first and not later in draw_vbo.

This fixes streamout where the "init" state, which disables streamout,
was emitted in draw_vbo after streamout was enabled.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-13 01:04:44 +02:00
Marek Olšák
2b0a54d6ec radeonsi: integrate shared streamout state
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-13 01:04:44 +02:00
Marek Olšák
4ea35023c5 radeon: don't emit streamout state if there are no streamout buffers
This could happen if set_stream_output_targets is called twice
in a row without a draw call in between.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-13 01:04:44 +02:00
Marek Olšák
60416cb173 radeon: don't emit VGT_STRMOUT_BUFFER_BASE on SI
The register doesn't exist on SI.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-13 01:04:44 +02:00
Christian König
2487324591 radeon/uvd: move more logic into the common files
Move the code back into the common UVD files since we now
have base structures for R600 and radeonsi.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-12 15:16:30 +02:00
Christian König
56be937d42 radeon/uvd: use more sane defaults for bitstream buffer size
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-12 15:16:06 +02:00
Andreas Boll
32637f56a5 os: First check for __GLIBC__ and then for PIPE_OS_BSD
Fixes FTBFS on kfreebsd-*

Debian GNU/kFreeBSD doesn't provide getprogname() since it uses stdlib.h
from glibc. Instead it provides program_invocation_short_name from glibc.

You can find the same order in src/mesa/drivers/dri/common/xmlconfig.c

Cc: "9.2" <mesa-stable@lists.freedesktop.org>
Tested-by: Julien Cristau <jcristau@debian.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-09-12 12:35:34 +02:00
José Fonseca
315f8f17d0 llvmpipe: Remove the special path for TGSI_OPCODE_EXP.
It was wrong for EXP.y, as we clamped the source before computing the
fractional part, and this opcode should be rarely used, so it's not
worth the hassle.
2013-09-12 11:24:24 +01:00
José Fonseca
e75211df0f trace: Several enhancements to dump_state.py
- Handle more calls
- Handle more state
- Try to normalize the output a bit, to eliminate spurious differences
2013-09-12 11:24:24 +01:00
José Fonseca
9641f1037c trace: Support bigger TGSI shaders.
Trivial.
2013-09-12 11:24:24 +01:00
Johannes Obermayr
5eb7ff1175 Move nv30, nv50 and nvc0 to nouveau.
It is planned to ship openSUSE 13.1 with -shared libs.
nouveau.la, nv30.la, nv50.la and nvc0.la are currently LIBADDs in all nouveau
related targets.
This change makes it possible to easily build one shared libnouveau.so which is
then LIBADDed.
Also dlopen will be faster for one library instead of three and build time on
-jX will be reduced.

Whitespace fixes were requested by 'git am'.

Signed-off-by: Johannes Obermayr <johannesobermayr@gmx.de>
Acked-by: Christoph Bumiller <christoph.bumiller@speed.at>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2013-09-11 21:47:07 +02:00
Johannes Obermayr
87ebbe1270 st/gbm: Add $(WAYLAND_CFLAGS) for HAVE_EGL_PLATFORM_WAYLAND. 2013-09-11 10:50:34 -07:00
Maarten Lankhorst
b217d48364 st/dri: do not create a new context for msaa copy
Commit b77316ad75
    st/dri: always copy new DRI front and back buffers to corresponding MSAA buffers

introduced creating a pipe_context for every call to validate, which is not required
because the callers have a context anyway.

Only exception is egl_g3d_create_pbuffer_from_client_buffer, can someone test if it
still works with NULL passed as context for validate? From examining the code I
believe it does, but I didn't thoroughly test it.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: 9.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-09-11 09:03:44 +02:00
Vinson Lee
49f2ba2cb0 radeonsi: Add parentheses around '|' operands.
Fixes GCC parentheses warning.

r600_texture.c: In function 'si_texture_create':
r600_texture.c:518:20: warning: suggest parentheses around arithmetic in operand of '|' [-Wparentheses]
      !(templ->bind & PIPE_BIND_CURSOR | PIPE_BIND_LINEAR)) {
                    ^

Fixes "Wrong operator used" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-09-10 10:44:09 -07:00
Vinson Lee
d93e23ba25 util: Fix unmatched parenthesis.
Fixes MSVC build error introduced with commit
923d346714.

src\gallium\auxiliary\util\u_cpu_detect.c(286) : fatal error C1012: unmatched parenthesis : missing '('

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
2013-09-10 10:33:47 -07:00
Brian Paul
923d346714 util: don't use _fxsave() with MSVC 2010 or older
And update _MSC_VER comments in p_config.h

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-09-10 11:01:37 -06:00
Chia-I Wu
e67f99bd29 ilo: preliminary GEN 7.5 support
This is based on grepping for brw->is_haswell in i965 to see how GEN 7.5
differs from GEN 7.  Slightly tested with Xonotic and some Mesa demos.
2013-09-08 01:22:52 +08:00
Alex Deucher
9bc47dbe50 r600g: remove DMA padding
This is now handled in the winsys.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-06 19:10:27 -04:00
Alex Deucher
a81beee37e radeon/winsys: pad IBs to a multiple of 8 DWs
This aligns the gfx, compute, and dma IBs to 8 DW boundries.
This aligns the the IB to the fetch size of the CP for optimal
performance. Additionally, r6xx hardware requires at least 4
DW alignment to avoid a hw bug.  This also aligns the DMA
IBs to 8 DW which is required for the DMA engine.  This
alignment is already handled in the gallium driver, but that
patch can be removed now that it's done in the winsys.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CC: "9.2" <mesa-stable@lists.freedesktop.org>
CC: "9.1" <mesa-stable@lists.freedesktop.org>
2013-09-06 19:08:35 -04:00
Axel Davy
e8f9195e5f gallium, intel: Implements new __DRI_IMAGE_USE_LINEAR and PIPE_BIND_LINEAR flags to enforce no tiling.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
2013-09-06 15:02:34 -07:00
Zack Rusin
e9f1f6ab42 gallivm: support indirect registers on both dimensions
We support indirect addressing only on the vertex index, but some
shaders also use indirect addressing on attributes. This patch
adds support for indirect addressing on both dimensions inside
gs arrays.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-09-06 15:05:27 -04:00
Stéphane Marchesin
f9b37f7183 i915g: Document fall-through switch
Fixes warning reported by Coverity.
2013-09-06 11:05:25 -07:00
Stéphane Marchesin
519a2cf950 i915g: Handle i915->batch == NULL correctly in flush
Fixes warning reported by Coverity.
2013-09-06 11:05:24 -07:00
Stéphane Marchesin
9e14895884 i915g: Remove useless comparison
Fixes "Macro compares unsigned to 0" defect reported by Coverity.
2013-09-06 11:05:24 -07:00
Stéphane Marchesin
7125af2957 i915g: Fix initial array index
Fixes "Out-of-bounds read" defect reported by Coverity.
2013-09-06 11:05:24 -07:00
Tom Stellard
505fad04f1 r600g/compute: Fix bug in compute memory pool
When adding a new buffer to the beginning of the memory pool, we were
accidentally deleting the buffer that was first in the buffer list.
This was caused by a bug in the memory pool's linked list
implementation.
2013-09-05 17:18:00 -07:00
Tom Stellard
f0435ebb07 r600g/compute: Don't flush the cs in pipe_context::launch_grid()
This is the state tracker's responsibility.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-09-05 17:17:43 -07:00
Ilia Mirkin
85f7df81a9 nv30: fix inconsistent setting of push->user_priv
It's set to &nv30->bufctx everywhere else.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
2013-09-05 20:46:56 +02:00
Stéphane Marchesin
8709e2b6c5 i915g: Implement writemask fixup
The fixup code emulates non-BGRA render targets by adding an
extra instruction at the end of fragment shaders to swizzle the
output. To do this, we also swizzle the blend function. However
an oversight until now was that the writemask wasn't getting
swizzled. This patch fixes that which fixes a bunch of piglit
tests.
2013-09-04 19:48:18 -07:00
Stéphane Marchesin
b1461acf15 i915g: Stop calling draw_prepare_shader_outputs
It's not useful on i915g since we don't support primid. Fixes
piglit point tests on i915g.
2013-09-04 19:48:18 -07:00
Stéphane Marchesin
4e861ac4a1 i915g: Add more optimizations
This patch adds liveness analysis to i915g and a couple
optimizations which benefit from it. One interesting
optimization turns (fake) indirect texture accesses into direct
texture accesses (the i915 supports a maximum of 4 indirect
texture accesses). Among other things this fixes a bunch of
piglit tests.
2013-09-04 12:11:02 -07:00
Michel Dänzer
6b5c802c30 radeonsi: Don't save/restore FMASK sampler view states for u_blitter
Fixes assertion failues in 24 piglit tests with
MESA_GL_VERSION_OVERRIDE=3.0, 12 of which are now passing.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-09-02 17:25:27 +02:00
Michel Dänzer
9933b85e12 radeonsi: Expose pure integer vertex formats
Fixes 20 piglit tests with MESA_GL_VERSION_OVERRIDE=3.0.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-09-02 17:25:27 +02:00
Maarten Lankhorst
ad4dc77231 nvc0: restore viewport after blit
Based on calim's original fix in the nine branch.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: "9.2 and 9.1" <mesa-stable@lists.freedesktop.org>
2013-09-02 17:09:21 +02:00
Christian König
3e81b8eedd radeon/uvd: save the aligned width & height
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=68845

Signed-off-by: Christian König <christian.koenig@amd.com>
2013-09-02 15:42:13 +02:00