Commit graph

39945 commits

Author SHA1 Message Date
Boris Brezillon
1b5873b73c panfrost: Use a pipe_framebuffer_state as the batch key
This way we have all the fb_state information directly attached to a
batch and can pass only the batch to functions emitting CMDs, which is
needed if we want to be able to queue CMDs to a batch that's not
currently bound to the context.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-09-13 16:25:06 +02:00
Indrajit Das
92765f85e1 radeon/vcn: exclude raven2 from vcn 2.0 encode initialization
Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2019-09-13 09:18:43 -04:00
Iago Toral Quiroga
2eace10c62 v3d: fix TF primitive counts for resume without draw
The V3D documentation states that primitive counters are reset when
we emit Tile Binning Mode Configuration items, which we do at the start
of each draw call, however, in the actual hardware this doesn't seem to
take effect when transform feedback is not active (this doesn't happen in
the simulator). This causes a problem in the following scenario:

glBeginTransformFeedback()
   glDrawArrays()
   glPauseTransformFeedback()
   glDrawArrays()
   glResumeTransformFeedback()
glEndTransformFeedback()

The TF pause will trigger a flush of the primitive counters, which results
in a correct number of primitives up to that point. In theory, the counter
should then be reset when we execute the draw after pausing TF, but that
doesn't happen, and since TF is enabled again by the resume command before
we end recording, by the time we end the transform feedback recording we
again check the counters, but instead of reading 0, we read again the same
value we read at the time we paused, incorrectly accumulating that value
again.

In theory, we should be able to avoid this by using the other method to
reset the primitive counters: using operation 1 instead of 0 when we
flush the counts to the buffer at the time we pause, but again, this
doesn't seem to be work and we still see obsolete counts by the time we
end transform feedback.

This patch fixes the problem by not accumulating TF primitive counts
unless we know we have actually queued draw calls during transform
feedback, since that seems to effectively reset the counters. This should
also be more performant, since it saves unnecessary stalls for the
primitive counters to be updated when we know there haven't been any
new primitives drawn.

Fixes CTS tests:
dEQP-GLES3.functional.transform_feedback.*

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-13 06:53:26 +00:00
Iago Toral Quiroga
ded6ea9209 v3d: remove redundant update of queued draw calls
This was updating the counter for the indexed draw path only, but we are
already updating the counter for all paths a bit later, so this is only
duplicating counts for indexed paths.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-13 06:53:26 +00:00
Iago Toral Quiroga
b9a07eed00 v3d: make sure we have enough space in the CL for the primitive counts packet
Fixes: 0f2d1dfe65 ("v3d: use the GPU to record primitives written to transform feedback")

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-13 06:53:26 +00:00
Iago Toral Quiroga
b69f51a5ef v3d: add missing line break for performance debug message
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-13 06:53:26 +00:00
Tomeu Vizoso
bc79e5c437 panfrost/ci: Use releases for Volt dEQP
So we can better correlate different results to versions of the runner.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-09-13 08:35:36 +02:00
Tomeu Vizoso
c301fc027a panfrost/ci: Update kernel to 5.3-rc8
We haven't updated in a long time, so better do it now and again when
5.3 is released.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-09-13 08:35:36 +02:00
Tomeu Vizoso
ca4e6637d0 panfrost/ci: Run dEQP with the surfaceless platform
Instead of running it with the Wayland platform, which introduces
unwanted dependencies and complexity.

Makes tests run 30% faster, as well.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-09-13 08:35:36 +02:00
Rob Clark
b4df115d3f freedreno/a6xx: pre-calculate userconst stateobj size
The AnTuTu "garden" benchmark overflows the fixed size constbuffer
stateobject, so lets be more clever and calculate (a potentially
slightly pessimistic) actual size.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-09-12 18:07:20 -07:00
Adam Jackson
5a9dec7534 gallium: Restore VSX for llvm >= 4
Accidentally dropped in 4fdd455eeb.

Fixes: 4fdd455e ("gallium: Require LLVM >= 3.4)
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-09-12 20:09:12 -04:00
Rob Clark
966b7c3ed2 freedreno: fix compiler warning
fd6_blitter.c:724:31: warning: passing argument 1 of ‘fd_resource_level_linear’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-12 12:52:04 -07:00
Eric Engestrom
f812cbfd88 meson/v3d: replace partial list of nir dep files with idep_nir_headers
"partial" because `nir_intrinsics_h` was missing.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-09-12 13:18:36 +01:00
Eric Engestrom
f418de5490 meson/iris: replace partial list of nir dep files with idep_nir_headers
"partial" because `nir_intrinsics_h` was missing.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-09-12 13:18:36 +01:00
Jose Maria Casanova Crespo
068c8889dd v3d: flag dirty state when binding compute states
As introduced in "v3d: flag dirty state when binding new sampler states"
we need to add support for compute states. New flag VC5_DIRTY_COMPTEX and
VC5_DIRTY_UNCOMPILED_CS are introduced.

Reaching 33 flags at the dirty field forces us to change the type to
uint_64. Flags are reordered and empty continuous bits are available
for future pipeline stages.

v2: Update flag conditions to compile cs shader. (Eric Antholt)
    Now dirty flags use uint_64t and flags are reordered.
    Added VC5_DIRTY_UNCOMPILED_CS flag.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-12 12:20:17 +01:00
Danylo Piliaiev
175c32e9bd tgsi_to_nir: Translate TGSI_INTERPOLATE_COLOR as INTERP_MODE_NONE
Translating TGSI_INTERPOLATE_COLOR as INTERP_MODE_SMOOTH made
it for drivers impossible to have flatshaded color inputs.

Translate it to INTERP_MODE_NONE which drivers interpret as
smooth or flat depending on flatshading state.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111467

Fixes: 770faf54 ("tgsi_to_nir: Improve interpolation modes.")

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-12 10:17:39 +00:00
Iago Toral Quiroga
7f0b4a803c gallium/ttn: VARYING_SLOT_PSIZ and VARYING_SLOT_FOGC are scalar
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-12 06:40:04 +00:00
Kenneth Graunke
6a82a374b4 iris: trivial whitespace fixes 2019-09-11 21:33:41 -07:00
Jonathan Marek
3690a53608 u_format: float type for R11G11B10_FLOAT/R9G9B9E5_FLOAT
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-09-11 22:39:19 -04:00
Jonathan Marek
8829f9ccb0 u_format: add ETC2 to util_format_srgb/util_format_linear
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-09-11 22:39:07 -04:00
Eric Anholt
272f9cfe6a dri: Use DRM_FORMAT_* instead of defining our own copy.
We have only two defines that aren't from DRM_FORMAT_*: SARGB and
SABGR.  Keep only those as __DRI_IMAGE_FOURCC and garbage collect the
rest.

While this header is also used from the X server, the X server doesn't
use any __DRI_IMAGE enums.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-09-11 13:05:10 -07:00
Anuj Phogat
729de1488f intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM
Initial benchmarking didn't show any performance benefits. But it might eventually.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-09-11 11:29:37 -07:00
Adam Jackson
96b592696f gallium: Require LLVM >= 3.9
To go any further than this would be to break the current version of
Android.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-09-11 17:00:43 +00:00
Adam Jackson
585d095610 gallium: Require LLVM >= 3.8
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-09-11 17:00:43 +00:00
Adam Jackson
59f18f2159 gallium: Require LLVM >= 3.7
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-09-11 17:00:43 +00:00
Adam Jackson
9abf7d5755 gallium: Require LLVM >= 3.6
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-09-11 17:00:43 +00:00
Adam Jackson
3c553d9cff gallium: Require LLVM >= 3.5
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

[ Michel Dänzer: Dropped jessie line from debian-install.sh again ]
2019-09-11 17:00:43 +00:00
Adam Jackson
4fdd455eeb gallium: Require LLVM >= 3.4
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-09-11 17:00:43 +00:00
Dylan Baker
52cf2d05a7 meson: don't generate file into subdirs
This is unsupported by meson and may become a hard error in the future.

Fixes: 5adfc8602c
       ("lima/ppir: move sin/cos input scaling into NIR")
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-09-11 08:35:05 -07:00
Kenneth Graunke
73b70b4952 iris: Set bo->reusable = false in iris_bo_make_external_locked
This fixes a missing bo->reusable = false in iris_bo_export_gem_handle.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2019-09-11 08:10:47 -07:00
Kenneth Graunke
06370c3167 iris: Finish initializing the BO before stuffing it in the hash table
Other threads may pick it up once it's in the hash table.  Not known
to fix anything currently.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2019-09-11 08:10:47 -07:00
Marek Olšák
9a59ad87df radeonsi/gfx9: honor user stride for imported buffers
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-11 11:03:31 -04:00
Marek Olšák
b97c5edd7a prog_to_nir, tgsi_to_nir: make sure kill doesn't discard NaNs
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-09-11 10:59:27 -04:00
Vasily Khoruzhick
32ea4c2c5e lima: set .out_sync field of req in lima_submit_start()
Looks like .out_sync wasn't set in lima_submit_start(), as result
submit completion fence was never signalled.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-09-10 21:49:53 -07:00
Kenneth Graunke
c6d40b5182 gallium: Fix util_format_get_depth_only
This is a pipe format, not a boolean.

Fixes: 5849e0612c ("gallium/auxiliary: Add util_format_get_depth_only() helper.")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-09-10 15:49:29 -07:00
Rob Clark
6c19d37331 freedreno/a6xx: fix 3d tex layout
Fixes dEQP-GLES3.functional.texture.specification.texstorage3d.size.3d_2x2x2_2_levels

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-09-10 22:08:33 +00:00
Rob Clark
85a23a8991 freedreno/a6xx: don't tile things that are too small
If the lowest (largest) mipmap level is too small to tile, then don't
bother pretending.

Note that this requires initializing pipe->screen before
fd_resource_level_linear() is called.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-09-10 22:08:33 +00:00
Caio Marcelo de Oliveira Filho
15e439071d iris: Enable ARB_gl_spirv and ARB_spirv_extensions
This will also "unlock" OpenGL 4.6 for Iris!

v2: Also enable PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [v1]
2019-09-10 14:36:46 -07:00
Caio Marcelo de Oliveira Filho
eca8032f20 gallium: Add ARB_gl_spirv support
The PIPE_CAP_GL_SPIRV capability enables ARB_gl_spirv and
ARB_spirv_extensions, and will make sure the corresponding SPIR-V
capabilities and extensions lists are initialized.

The additional PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS capability enables
the support for Variable Pointers in SPIR-V shaders.  This depends on
the driver and is not mandatory for ARB_gl_spirv support.

v2: Add a PIPE_CAP for Variable Pointers.  (Marek)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [v1]
2019-09-10 14:36:46 -07:00
Kenneth Graunke
077a1952cc iris: Fix constant buffer sizes for non-UBOs
Since the system value refactor, we've accidentally only been setting
cbuf->buffer_size in the UBO case, and not in the uploaded-constants
case.  We use cbuf->buffer_size to fill out the SURFACE_STATE entry,
so it needs to be initialized in both cases.

Fixes: 3b6d787e40 ("iris: move sysvals to their own constant buffer")
2019-09-10 10:53:15 -07:00
Marek Olšák
ef919d8dcb radeonsi: remove redundant si_texture offset and size fields
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
e4c84d8678 radeonsi: move texture storage allocation outside of radeonsi
possible code sharing with radv

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
58ccadfc5c radeonsi: move HTILE allocation outside of radeonsi
ac_surface computes it for amdgpu.
radeon_drm_surface computes it for radeon.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
30a1dd0ee6 radeonsi: handle NO_DCC early
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
7d4a10a29f ac/surface: add RADEON_SURF_NO_FMASK
This controls FMASK and CMASK computation for MSAA.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
6633863150 r300,r600,radeonsi: set winsys_handle::stride,offset in drivers, not winsyses
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
5ac6908263 r300,r600,radeonsi: read winsys_handle::stride,offset in drivers, not winsyses
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
d95afd8b9e radeonsi/gfx10: fix wave occupancy computations
Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
42ea0b7b52 radeonsi: only support at most 1024 threads per block
LLVM 10 won't support 2048.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
c1e08cb6d5 radeonsi: disable DCC when importing a texture from an incompatible driver
and unify the code.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00