Commit graph

67748 commits

Author SHA1 Message Date
Timur Kristóf
f5981e8c0b ac/nir: Split GS output usage masks to varying and sysval masks.
To keep track which output is used for what purpose.

Note that this commit just adds the capability to track this
separately in ac/nir. The drivers will need to be updated
in the future to take advantage of this.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32640>
2024-12-28 10:31:33 -06:00
David Rosca
a642ff15a6 frontends/va: Fix deinterlace filter
Deinterlace filter uses interlaced buffer for output which needs
to be converted to progressive. Add back code that handles this.

Fixes: c324364f39 ("frontends/va: Only use interlaced surfaces when progressive is not supported")
Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32768>
2024-12-28 12:02:42 +00:00
Qiang Yu
403cdacaff radeonsi: replace ac_nir_lower_subdword_loads
ac_nir_lower_mem_access_bit_sizes() does the work of it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32781>
2024-12-27 01:58:38 +00:00
Qiang Yu
955ae53efd radeonsi: fix OpenCL piglit tests fails when using ACO
Now no regression compared with using LLVM.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32781>
2024-12-27 01:58:38 +00:00
Qiang Yu
9a8eef282b radeonsi: fix OpenCL shader compile fail
sel->stage is assigned with MESA_SHADER_COMPUTE statically,
change to use nir->info.stage need to handle with MESA_SHADER_KERNEL.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12372
Fixes: 9b7ea720c9 ("radeonsi: use nir->info instead of sel->info.base")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32781>
2024-12-27 01:58:38 +00:00
Marek Olšák
47cdec24ee radeonsi: remove unused code
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32780>
2024-12-26 10:12:43 +00:00
Marek Olšák
357ee7f699 radeonsi: switch si_get_blitter_vs to IO intrinsics
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32780>
2024-12-26 10:12:43 +00:00
Marek Olšák
a0579f75fb radeonsi: fix a TCS regression
This change caused the regression:
@@ -853,7 +853,7 @@ bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *

       /* Reset the shader context. */
       ctx.shader = shader;
-      ctx.stage = sel->stage;
+      ctx.stage = nir->info.stage;

       bool same_thread_count = shader->key.ge.opt.same_patch_vertices;
       si_build_wrapper_function(&ctx, parts, same_thread_count);

because "nir" contains the previous shader (LS), not the current shader (HS).
Fix it by using prev_nir for the previous shader, so that we can keep using
"nir".

Fixes: 9b7ea720c9 - radeonsi: use nir->info instead of sel->info.base

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32780>
2024-12-26 10:12:43 +00:00
Marek Olšák
227a894775 radeonsi/ci: update failures
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32780>
2024-12-26 10:12:43 +00:00
Marek Olšák
af899c3752 radeonsi,radv: fix incorrect min_esverts for NGG subgroup calculation
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
c52025a1ce radeonsi: disable luminance alpha formats on gfx6
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
9b7ea720c9 radeonsi: use nir->info instead of sel->info.base
sel->info is out of date after shader variant optimizations. We need to
stop using it.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
04a0800068 radeonsi: call si_init_shader_args in si_get_nir_shader
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
409a6fd69c radeonsi: make si_init_shader_args static
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
7ddb28f447 radeonsi: remove some uses of enum pipe_shader_type
it's identical to gl_shader_stage

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
110b308841 radeonsi: make nir->info and si_shader_info::base identical
so that we can use nir->info instead of the latter.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
6a1bdf2f78 radeonsi/gfx12: tune streamout performance
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
10b951d752 radeonsi/gfx12: fix DrawTransformFeedback(stream != 0)
We only set buf_filled_size for the first target, but draws from non-zero
streams use buf_filled_size from other targets, so share the same
buf_filled_size buffer among all streamout targets because it contains
all 4 offsets.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
8440184dfd radeonsi: make NGG streamout output primitive type known at compile time
This compiles an optimized shader variant for NGG streamout where the output
primitive is known at compile time. This allows putting stores for all
vertices into the same VMEM clause.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
5003465c42 radeonsi: eliminate shader code computing killed Z/S/samplemask PS outputs
Compile a monolithic optimized shader to do that, and clean up the comments.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
58132d6fc8 radeonsi: implement nir_opt_frag_depth using kill_z instead of the NIR pass
This uses si_shader_info to store whether gl_FragDepth can be removed,
and it uses the kill_z epilog flag to do the removal without recompilation.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
b56f47611a radeonsi: fix alpha-to-coverage + alpha-to-one used together for gfx6-10.3
It works exactly like gfx11 except that COVERAGE_TO_MASK_ENABLE must be 1
to indicate that alpha for alpha-to-coverage should be read from mrtz.a.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
08abddd235 radeonsi/gfx11: fix alpha-to-coverage + alpha-to-one used together
alpha-to-coverage must be applied before alpha-to-one. The only way to do
that is to export alpha for alpha-to-coverage via mrtz, and export 1 via
mrt0.a.

ACO and monolithic shader support is already in place thanks to RADV,
so we only need to change the LLVM PS epilog and the shader key.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
de996ac481 radeonsi: kill Z and stencil PS outputs if depth or stencil is disabled
This adds kill_z and kill_stencil flags to the shader PS epilog key, which
removes those outputs if depth or stencil are disabled.

It must be implemented in:
* ACO PS epilog
* LLVM PS epilog
* ac_nir_lower_ps for monolithic shaders

Some of the samplemask code wasn't completely correct, but probably harmless.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
0beeb16e41 radeonsi: fix a gfx10.3 regression due to a gfx12 change
This fixes:
    Assertion `!"BITSET_TEST_RANGE: bit range crosses word boundary"' failed.

Fixes: e3cef02c24 - radeonsi/gfx12: set DB_RENDER_OVERRIDE based on stencil state

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
4ee1b2ee24 radeonsi/ci: update failures and flakes
If deqp-runner detects a flake, it's not reported without -v.
Here I gathered all the flakes.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Marek Olšák
31358df708 radeonsi/ci: don't copy skips.csv to the results directory
It's not needed anymore. This fixes the script for llvmpipe.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:20 +00:00
Pierre-Eric Pelloux-Prayer
c0ef2aa7f8 DEPENDENCY: ac/llvm: fix sparse code handling
The existing code produced a incorrectly sized result from visit_tex.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32713>
2024-12-24 12:02:19 +00:00
Marek Olšák
3a7737ffb5 virgl/ci: disable virgl-traces because it doesn't upload results
Not being able to review results makes it impossible to update the hashes.

Suggested by Daniel Stone.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31942>
2024-12-24 05:54:07 -05:00
Marek Olšák
73d675451b ci: update fail lists and trace checksums
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31942>
2024-12-24 05:54:07 -05:00
Marek Olšák
4932b63f36 v3d: enable uniform expression propagation from outputs to the next shader
This will take effect after nir_opt_varyings is enabled by another MR, and
will fix existing shader compiler crashes thanks to better optimizations.

For example, one GLSL program that failed to compile and had 226 VS
instructions and 356 FS instructions in NIR will be reduced to 2 or 3
instructions per shader.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31942>
2024-12-24 05:54:07 -05:00
Rohan Garg
5bddf6ceb0 iris: assert that we're not exporting a TILE64 surface
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32771>
2024-12-23 19:33:36 +00:00
Rohan Garg
abd137d079 iris: use CALLOC_STRUCT instead of calloc for readability
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32771>
2024-12-23 19:33:36 +00:00
Juan A. Suarez Romero
4226be0c75 vc4: ensure sharing tiled resources are of proper format
When creating a tiled resource, it could be created either with "T" or
"LT" format.

But when sharing the resource, only "T" format is appropiate. So we need
to perform a conversion if required.

This is based on
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32661.

Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32703>
2024-12-23 13:08:43 +00:00
Samuel Pitoiset
47dc9ca512 radv: rework emitting SPI_SHADER_Z_FORMAT
This fixes a small issue when the Z format in PS epilogs change, like
when alpha-to-coverage is enabled and then disabled.

igned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32675>
2024-12-23 08:09:26 +00:00
David Rosca
ed58b869e1 frontends/va: Don't allow EndPicture without calling driver begin_frame
This can happen in decode context when application send no slice
buffers or in processing context with no processing buffers.
We need to avoid calling driver end_frame as no begin_frame will be
called in this case.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32677>
2024-12-21 09:34:01 +00:00
David Rosca
42e765d48b frontends/va: Don't allow Render/EndPicture without BeginPicture
It's not valid to call RenderPicture and EndPicture without calling
BeginPicture or when BeginPicture fails. FFmpeg will however call
EndPicture when BeginPicture fails, so we need to handle this.
Use target_id, which is assigned in BeginPicture, as an indication
whether we are inside the Begin - End picture sequence.

Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32677>
2024-12-21 09:34:01 +00:00
David Rosca
6e911cf252 frontends/va: Fix decoding VC1 interlaced video
VC1 has different start code for FRAME and FIELD, so we need to use
FIELD start code for second field.
Also simplify start code search to only look for 00 00 01.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2347
Cc: mesa-stable
Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32741>
2024-12-21 08:54:41 +00:00
Patrick Lerda
ad5c47502d r600: reverse fix spec ext_packed_depth_stencil getteximage
This change reverses d19e2597ce which is now superseded on the mesa
development branch by 42be38a8fb ("radeon/evergreen: ensure equal
sizes for depth-stencil npot textures").

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: David Heidelberg <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32553>
2024-12-21 05:07:16 +00:00
Alyssa Rosenzweig
a3b796ba19 libagx,hk: handle pipeline stats queries without a GS
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:32 +00:00
Alyssa Rosenzweig
7626e40506 asahi: reformat
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Alyssa Rosenzweig
b6dbfe822b asahi: use common draw
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32759>
2024-12-21 01:50:31 +00:00
Eric R. Smith
4533144608 panfrost: apply DEPTH_STENCIL flag consistently
We were inconsistent over the usage of PAN_BIND_DEPTH_STENCIL, putting
it on some stencil only formats but not others. Apply it to all
stencil formats. However, we also need to change is_format_supported
to ignore S8_UINT (at least for GLES), because the hardware is a little
weird with that format and the gallium driver gets confused by it.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32462>
2024-12-20 23:18:08 +00:00
nyanmisaka
8a5ec60442 frontends/vdpau: Get AV1 decode subsampling_x/y
The VDPAU frontend requires similar changes as in the VAAPI frontend.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12337

Signed-off-by: nyanmisaka <nst799610810@gmail.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32752>
2024-12-20 16:36:42 +00:00
David Rosca
5621ce10a6 radeonsi/vcn: Return error when decoding 12bit VP9 and 4:2:2/4:4:4 AV1
This is not supported by VCN.
We indicate this limitation by not reporting YUV420_12 RT format
supported for VP9, and not reporting YUV422 and YUV444 for AV1.
Most applications however simply ignore this, and will pick some other
format that is supported, which obviously won't work.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32663>
2024-12-20 10:51:18 +00:00
David Rosca
245d8c8e99 frontends/va: Get AV1 decode subsampling_x/y
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32663>
2024-12-20 10:51:18 +00:00
David Rosca
d94597a2d8 pipe: Remove PIPE_DEFAULT_DECODER_FEEDBACK_TIMEOUT_NS
Use OS_TIMEOUT_INFINITE instead.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32705>
2024-12-20 11:19:49 +01:00
David Rosca
c03805e4f5 radeonsi/vcn: Use local variable for destory fence
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32705>
2024-12-20 11:19:05 +01:00
David Rosca
fed1ed1eff radeonsi/vcn: Don't keep last fence
This is not needed after 0c024bbe64 ("radeonsi/vcn: Add decode DPB buffers as CS dependency")

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32705>
2024-12-20 11:18:23 +01:00
Peyton Lee
ad0dbea49d radeonsi/vpe: add destroy_fence function
implement destroy_fence() for better fence control

Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32648>
2024-12-20 09:55:00 +00:00