Commit graph

16394 commits

Author SHA1 Message Date
Georg Lehmann
0b9e2a5427 aco/ra: disallow s_cmpk with scc operand
Fixes: 2d6b0a4177 ("aco/optimizer: Optimize SOPC with literal to SOPK.")

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32545>
2024-12-11 12:51:18 +00:00
Georg Lehmann
fe0c72caec aco/ra: don't write to exec/ttmp with mulk/addk/cmovk
ttmp sgprs are readonly outside of trap handlers, so the instructions were
probably skipped. RA should also never create additional exec writes.

Fixes: e06773281b ("aco/ra: Optimize some SOP2 instructions with literal to SOPK.")

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32545>
2024-12-11 12:51:18 +00:00
Georg Lehmann
576a2e798c aco/gfx12: don't assume memory operations complete in order
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32569>
2024-12-11 12:22:59 +00:00
Samuel Pitoiset
553eb1a3fd radv: fix alpha-to-coverage with alpha-to-one when MRTZ is also exported
On AMD hardware, it's possible to export a separate alpha channel for
applying alpha-to-one after alpha-to-coverage and not before.

On GFX11+, it's already mostly supported but alpha needs to be exported
to MRTZ.a and one to MRT0.a. The hw always uses alpha for
alpha-to-coverage from MRTZ.a.

On older generations, the driver needs the same separate alpha export
but it also needs to configure the hardware with COVERAGE_TO_MASK_ENABLE
which selects alpha from MRTZ.a.

This should fix alpha-to-coverage with alpha-to-one when either
depth, stencil or samplemask are exported but it still needs a slightly
different solution without MRTZ. I will fix that later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32523>
2024-12-11 10:50:31 +00:00
Samuel Pitoiset
70047e6bd6 aco: export alpha to MRTZ.a and one to MRT0.a for alpha-to-one on GFX11
For FS epilogs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32523>
2024-12-11 10:50:31 +00:00
Samuel Pitoiset
1037830098 ac/nir: export alpha to MRTZ.a and one to MRT0.a for alpha-to-one on GFX11
When alpha-to-coverage and alpha-to-one are both enabled in the
fragment shader, the alpha value should be exported through MRTZ and
one to MRT0.a. Otherwise, alpha-to-one will be performed before
alpha-to-coverage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32523>
2024-12-11 10:50:31 +00:00
Samuel Pitoiset
3b010a9e60 radv: disable alphaToOne except for Zink
It's just completely broken if alpha-to-coverage is also used. Given
this is a requirement for Zink and no known GL apps are affected, let's
disable for everything except Zink. This is going to be fixed but the
fixes aren't small enough for backporting.

This fixes a rendering issue with XPlane 12.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32576>
2024-12-11 08:28:25 +00:00
Samuel Pitoiset
310e03c8d3 radv/meta: move vk_meta_device_init() to radv_device_init_meta()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32571>
2024-12-11 07:25:29 +00:00
Samuel Pitoiset
cad6e1ea09 radv/meta: add missing vk_meta_device_finish()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32571>
2024-12-11 07:25:29 +00:00
Martin Roukala (né Peres)
b8054556a0 radv/ci: update the vkcts expectations
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32541>
2024-12-11 04:24:35 +00:00
Dave Airlie
699afb88ec radv/video: set max slice counts to 1 for h264/5 encode
Right now the driver doesn't support multi-slice encodes, so
report the correct value.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Autumn Ashton
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32580>
2024-12-11 01:11:32 +00:00
Georg Lehmann
7bb3f93fa9 radv: use nir_opt_clip_cull_const
This reduces the fixed function hardware bottleneck in vertex shading
heavy sections with d3d9 DXVK.

DXVK always declares 6 clip distances, and with
https://github.com/doitsujin/dxvk/pull/4508
it writes 0 for disabled clip planes.

But while working on this, I also discovered that other games also write
constant clip/cull distances:

Foz-DB Navi21:
Totals from 442 (0.56% of 79206) affected shaders:
MaxWaves: 10880 -> 10900 (+0.18%)
Instrs: 283569 -> 282493 (-0.38%); split: -0.38%, +0.01%
CodeSize: 1497596 -> 1491948 (-0.38%); split: -0.38%, +0.00%
VGPRs: 18928 -> 18888 (-0.21%)
Outputs: 3026 -> 2970 (-1.85%)
Latency: 1051990 -> 1048878 (-0.30%); split: -0.47%, +0.18%
InvThroughput: 184190 -> 183366 (-0.45%); split: -0.45%, +0.01%
VClause: 6071 -> 6077 (+0.10%); split: -0.38%, +0.48%
SClause: 6724 -> 6725 (+0.01%); split: -0.12%, +0.13%
Copies: 19624 -> 19160 (-2.36%); split: -2.44%, +0.08%
PreSGPRs: 18634 -> 18526 (-0.58%)
PreVGPRs: 15522 -> 15465 (-0.37%)
VALU: 156964 -> 156330 (-0.40%); split: -0.41%, +0.01%
SALU: 41802 -> 41748 (-0.13%); split: -0.13%, +0.00%

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32518>
2024-12-10 16:35:01 +00:00
Georg Lehmann
4f88dbffa4 radv: track holes in the clip/cull masks
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32518>
2024-12-10 16:35:01 +00:00
Georg Lehmann
4a977ea24f aco/gfx11+: use v_and_b32 to extract local id 0
Foz-DB Navi31:
Totals from 2561 (3.23% of 79206) affected shaders:
CodeSize: 10399004 -> 10389120 (-0.10%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32532>
2024-12-10 11:58:21 +00:00
Samuel Pitoiset
a653654b8d radv: dump the Mesa version with RADV_DEBUG=hang
This was missing and it can be very useful to know.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32560>
2024-12-09 18:25:24 +00:00
Samuel Pitoiset
9d2b548825 radv: only dump device name info on Linux with RADV_DEBUG=hang
Doesn't make sense on Windows.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32560>
2024-12-09 18:25:24 +00:00
Samuel Pitoiset
e3d1f27b31 radv: add radv_disable_dcc_stores and enable for Indiana Jones: The Great Circle
Likely a game bug but can't be 100% sure because the game uses RT by
default and renderdoc still doesn't have support for it.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32528>
2024-12-09 17:52:43 +00:00
Rhys Perry
033e76a82a ac/nir: have ac_nir_lower_mem_access_bit_sizes preserve >128 bit SMEM
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32408>
2024-12-09 16:56:29 +00:00
Rhys Perry
77f8436c62 radv: skip loading unused push constants
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32408>
2024-12-09 16:56:29 +00:00
Rhys Perry
2e63da865b radv: fix expanded push constant loads when all are inlined
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32408>
2024-12-09 16:56:29 +00:00
Rhys Perry
0ccea63b6a radv: constant fold after lowering memory accesses
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32408>
2024-12-09 16:56:29 +00:00
Valentine Burley
4379545117 amd/ci: Increase fraction for radeonsi-raven-piglit
This job was taking longer than 10 minutes, so increase the
fraction of the quick_shader piglit profile to get the runtime
within acceptable limits.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32455>
2024-12-09 15:18:37 +00:00
Valentine Burley
a3d599e932 amd/ci: Convert LAVA RADV jobs to deqp-runner suites
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32455>
2024-12-09 15:18:37 +00:00
Valentine Burley
63b4765114 amd/ci: Merge and convert Raven piglit testing
Converting to deqp-runner suite allows merging the two jobs running
the two piglit profiles for more even distribution and granular
control of runtime.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32455>
2024-12-09 15:18:37 +00:00
Valentine Burley
e26391f7ff amd/ci: Drop x86_64 suffix from job names
These added no value and made the names unnecessarily long.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32455>
2024-12-09 15:18:36 +00:00
Lionel Landwerlin
877a296b2c vulkan: make acceleration structure debug markers virtual
Not every implementation supports VK_EXT_debug_marker.
VK_EXT_debug_utils is also pretty similar, it would be nice to plug
into whatever is available.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32483>
2024-12-09 14:45:00 +00:00
Alyssa Rosenzweig
972f8aa287 vulkan: rename depth bias graphics states
"constant" is a special keyword in OpenCL C, and we'd like to #define it
suitably in host C23 to facilitate compatiblity between host/device headers.
That means we can't have any identifiers named "global" or "constant".
Fortunately, this is the only 'constant' in any file I'm hitting.

To avoid the clash, don't abbreviate "constant factor", use "constant_factor"
instead. For consistency, "slope factor" then becomes "slope_factor".
The new names are longer but match the Vulkan API exactly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> [Intel]
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com> [NVK and panvk]
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [V3DV]
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com> [IMG]
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32505>
2024-12-06 13:48:26 -05:00
Daniel Schürmann
b64fff7731 aco: remove definition from Pseudo branch instructions
They are not needed anymore.

Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)

Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-12-06 14:34:03 +00:00
Daniel Schürmann
7e4687fd04 aco: remove definition from SOPP branch instructions
Totals from 17942 (22.60% of 79395) affected shaders: (Navi31)

Instrs: 20334063 -> 20312676 (-0.11%); split: -0.11%, +0.00%
CodeSize: 108458732 -> 108377540 (-0.07%); split: -0.08%, +0.00%
Latency: 180510540 -> 180479666 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 28079325 -> 28077938 (-0.00%); split: -0.01%, +0.00%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-12-06 14:34:03 +00:00
Daniel Schürmann
cab5639a09 aco/assembler: chain branches instead of emitting long jumps
As regular branch instructions cannot jump further than
32768 dwords, previously we used long jumps as fallback
solution. The disadvantage of that is that an extra SGPR
pair must be provided in order to temporarily store the PC.

This patch changes that to chained branch instructions by
inserting an artificial extra block into the code to be
targeted by the original branch. This block contains a
single branch instruction jumping to the original target.
Before the block, if necessary, we insert a <branch 1>
instruction for the existing code in order to jump over
the newly inserted block.

Only a few RT shaders are affected.

Totals from 29 (0.04% of 79395) affected shaders: (Navi31)

CodeSize: 17281176 -> 17276332 (-0.03%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-12-06 14:34:03 +00:00
Daniel Schürmann
c3d777d8ac aco/assembler: change ctx.loop_header to uint32_t instead of Block*
We are about to add new blocks during assembly which makes
pointers into a vector unreliable.
Also, only set it if the loop has no back-edge.

Totals from 126 (0.16% of 79206) affected shaders: (Navi31)

CodeSize: 1486152 -> 1488152 (+0.13%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-12-06 14:34:03 +00:00
Daniel Schürmann
592f3fd994 aco/assembler: Actually insert s_inst_prefetch instructions when aligning blocks for loops
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-12-06 14:34:03 +00:00
Daniel Schürmann
b92afdbd28 aco/assembler: constify assembly functions
Ensure that instruction formats and special operands
are not manipulated during assembly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-12-06 14:34:03 +00:00
Daniel Schürmann
3a02bbd916 aco/print_asm: allow for empty blocks with arbitrary offsets
We will add empty blocks at the end of the shader,
in order to store some branch offset information.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-12-06 14:34:03 +00:00
Rhys Perry
ab26b99c2c aco: don't CSE p_shader_cycles_hi_lo_hi
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: fae2a85d57 ("aco/gfx12: implement subgroup shader clock")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12243
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32500>
2024-12-06 14:06:05 +00:00
Georg Lehmann
da4b9ac4a5 radeonsi/ci: add vangogh ubo fail
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32522>
2024-12-06 12:58:47 +00:00
Georg Lehmann
b2464e3609 aco/gfx12+: do not use v_pack_b32_f16 to pack untyped data
GFX12 removed IEEE_MODE, and made its signalling NaN quieting the default.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12251
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32502>
2024-12-06 12:33:05 +00:00
Georg Lehmann
7425e71ae0 aco/gfx12: disable vinterp ddx/ddy optimization
This only seems to work on gfx11 and gfx11.5, and it's only faster on gfx11.5.

We could continue to use vinterp, with constants copied to vgprs, but
whether that's beneficial depends on the shader.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

Fixes: bee487df48 ("aco/gfx11.5+: use vinterp for fddx/fddy")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12250
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32495>
2024-12-06 12:01:39 +00:00
Samuel Pitoiset
6b671d4dab radv: remove redundant drirc for incorrect dual-source blending
The pass that lowers PS outputs has been rewritten since 45d8cd037a
("ac/nir: rewrite ac_nir_lower_ps epilog to fix dual src blending
with mono PS") to handle invalid uses of dual-source blending.

This drirc used to workaround game bugs on GFX11 only should no longer
be necessary.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32514>
2024-12-06 07:54:23 +00:00
Samuel Pitoiset
ea112cf84d ci: update VKCTS main to a9f7069b9a5ba94715a175cb1818ed504add0107
This contains many more tests for Vulkan 1.4, but the Vulkan loader
probably needs an update too.

This should only affect RADV which is the only user for VKCTS main.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32475>
2024-12-05 08:06:23 +00:00
Samuel Pitoiset
8b755840fc radv: fix initializing HTILE when the image has VRS rates
VRS rates should only be preserved for clears, otherwise the HTILE
buffer should be cleared completely.

This fixes some failures/flakes in CI.

Fixes: 8197d744f5 ("radv: Do not overwrite VRS rates when doing fast clears")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32463>
2024-12-05 07:34:58 +00:00
Samuel Pitoiset
e73fdac9a6 radv: enable DGC IES for compute with ESO
This was supposed to be enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32484>
2024-12-05 07:06:17 +00:00
Marek Olšák
943360c86b amd/ci: add piglit failures due to a overzealous test
It's missing: https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/976

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32424>
2024-12-04 13:40:41 +00:00
Marek Olšák
d8468d5463 amd,zink: remove options.varying_estimate_instr_cost callbacks
They are a maintainenance burden since they would need changes to
support more instruction types that nir_opt_varyings will be able to
move between shaders, and they are almost identical to
default_varying_estimate_instr_cost, so just use that.

The cost threshold is adjusted for AMD because
default_varying_estimate_instr_cost is slightly different.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32424>
2024-12-04 13:40:41 +00:00
Samuel Pitoiset
5d072e0e73 radv: fix stencil only copies of depth/stencil images with SDMA
This was broken for two reasons:
- the number of bytes per element should be 1 (8-bit for stencil)
- the base offset should be adjusted for the stencil

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32459>
2024-12-04 09:30:36 +00:00
Autumn Ashton
7e9ea5c1b5 radv/video: Fix bitstreamStartOffset including dstBufferOffset
The bitstreamStartOffset from the VK_QUERY_TYPE_VIDEO_ENCODE_FEEDBACK_KHR query in RADV is currently relative to the dstBuffer, and not dstBuffer + dstBufferOffset like the spec states.

To fix this, let's append the offset to the VA directly and not tell the encoder about the offset relative to the VA at all.

The Vulkan spec states:
"VK_VIDEO_ENCODE_FEEDBACK_BITSTREAM_BUFFER_OFFSET_BIT_KHR specifies that queries managed by the pool will capture the byte offset of the bitstream data written by the video encode operation to the bitstream buffer specified in VkVideoEncodeInfoKHR::dstBuffer relative to the offset specified in VkVideoEncodeInfoKHR::dstBufferOffset."

The relevant part being that is is relative to dstBufferOffset and not the start of the VkBuffer.

Signed-off-by: Autumn Ashton <misyl@froggi.es>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32452>
2024-12-03 22:19:43 +00:00
Georg Lehmann
1a7ebfd2a8 radv: rework vk_property initialization
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32457>
2024-12-03 21:43:34 +00:00
Georg Lehmann
b961537a17 radv: fix reporting mesh/task/rt as supported dgc indirect stages
Fixes: 8300378bf3 ("radv: advertise VK_EXT_device_generated_commands on GFX8+")

Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32457>
2024-12-03 21:43:34 +00:00
Samuel Pitoiset
9df3c9e4a1 ac/parse_ib: print VA for the SDMA CONSTANT_FILL/WRITE packets
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32456>
2024-12-03 15:29:40 +00:00
Samuel Pitoiset
31524d42a2 ac/parse_ib: fix parsing SDMA CONSTANT_FILL packet
This packet only has 5 DWORDS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32456>
2024-12-03 15:29:39 +00:00