Commit graph

32051 commits

Author SHA1 Message Date
Marek Olšák
068c3ad2cb gallium: remove TGSI FENCE opcodes
use MEMBAR instead

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
44716655e6 gallium: remove TGSI opcodes PUSHA, POPA, SAD, TXQ_LZ
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
8dadb07790 radeonsi: emit VGT_REUSE_OFF in the right place
clip_regs aren't marked dirty when writes_viewport_index is changed.

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
a6fed63f27 radeonsi: add support for TGSI opcodes DCEIL, DFLR, DROUND, DSSG, DTRUNC
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
addd48194a radeonsi: use a faster version of PK2H
+ 4 piglit regressions, but it's correct accorcing to the GL spec and
performance is more important than piglit.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
dc2ac03669 radeonsi: don't decompress Z/S if there is no HTILE
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
e96259fabe gallium/radeon: add helpers for whether HTILE is enabled
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
7dec48b81e radeonsi/gfx9: don't flush L2 metadata for DB if not needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
aa64e24cb1 radeonsi/gfx9: don't flush L2 metadata for CB if not needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
5b62eb237c radeonsi/gfx9: don't flush TC L2 between rendering and texturing if not needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
287b0a28f4 radeonsi/gfx9: use correct TC flush flags when invalidating CB & DB
Now we can finally stop flushing L2 data.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
54c2c771bd radeonsi/gfx9: don't use GS scenario A for VS writing ViewportIndex
Vulkan doesn't do it anymore.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
776fcccabf gallium/radeon: clean up EOP_DATA_SEL magic numbers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
a57f588fa9 radeonsi/gfx9: set 'not a query' for r600_gfx_write_event_eop correctly
0 is PIPE_QUERY_OCCLUSION_COUNTER, which is not what we want.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
a65afda768 radeonsi/gfx9: prevent shader-db crashes
- don't precompile LS and ES (they don't exist on GFX9), compile as VS instead
- don't precompile HS and GS (we don't have LS and ES parts)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
fdef2f0fd1 radeonsi/gfx9: properly handle imported textures with unexpected swizzle mode
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
113278ee79 radeonsi: remove Constant Engine support
We have come to the conclusion that it doesn't improve performance.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
166823bfd2 radeonsi/gfx9: add a temporary workaround for a tessellation driver bug
The workaround will do for now. The root cause is still unknown.

This fixes new piglit: 16in-1out

Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Samuel Pitoiset
39a35eb0c1 radeonsi: try to re-use previously deleted bindless descriptor slots
Currently, when the array is full it is resized but it can grow
over and over because we don't try to re-use descriptor slots.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:37 +02:00
Samuel Pitoiset
c2dfa9b111 radeonsi: use slot indexes for bindless handles
Using VRAM address as bindless handles is not a good idea because
we have to use LLVMIntToPTr and the LLVM CSE pass can't optimize
because it has no information about the pointer.

Instead, use slots indexes like the existing descriptors. Note
that we use fixed 16-dword slots for both samplers and images.
This doesn't really matter because no real apps use image handles.

This improves performance with DOW3 by +7%.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:29 +02:00
Samuel Pitoiset
50349f404d radeonsi: add si_emit_global_shader_pointers() helper
To share common code between rw buffers and bindless descriptors.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:24 +02:00
Samuel Pitoiset
a5ff4a8e2e radeonsi: only initialize dirty_mask when CE is used
Looks like it's useless to initialize that field when CE is
unused. This will also allow to declare more than 64 elements
for the array of bindless descriptors.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:23 +02:00
Samuel Pitoiset
a29ef75565 radeonsi: make some si_descriptors fields 32-bit
The number of bindless descriptors is dynamic and we definitely
have to support more than 256 slots.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:21 +02:00
Samuel Pitoiset
781a13c475 radeonsi: declare new user SGPR indices for bindless samplers/images
A new pair of user SGPR is needed for loading the bindless
descriptors from shaders. Because the descriptors are global for
all stages, there is no need to add separate indices for GFX9.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:15 +02:00
Samuel Pitoiset
e2793def40 gallium/util: add new module that allocate "numbers"
Will be used for allocating bindless descriptor slots for
RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:04 +02:00
Nicolai Hähnle
472c906d9f radeonsi/gfx9: add performance counters
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:55:16 +02:00
Nicolai Hähnle
e271607668 radeonsi: extract common code of si_upload_{graphics,compute}_shader_descriptors
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:55:05 +02:00
Nicolai Hähnle
a6e7693882 gallium: remove unused PIPE_DUMP_* defines
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:53:35 +02:00
Nicolai Hähnle
635a930ad3 ddebug: remove dd_draw_record::driver_state_log
It is no longer used.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:53:35 +02:00
Nicolai Hähnle
f4c1d5a76d radeonsi: emit string markers to log context
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:53:34 +02:00
Nicolai Hähnle
0c3f8aca7f radeonsi: log decompress blits
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:53:34 +02:00
Nicolai Hähnle
420c438589 radeonsi: log draw and compute state into log context
Also add missing trace emits and CS logging for compute launches.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:53:34 +02:00
Nicolai Hähnle
4c3f36ec6b radeonsi: print saved CS to the log context
Use the auto logger facility, so that CS chunks will be interleaved
with other log info.

v2:
- fix some crashes when not using CE
- fix skipping "previous" chunks of current (unflushed) IB
- fix error handling in si_begin_cs_debug

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:53:14 +02:00
Nicolai Hähnle
bc93339799 radeonsi: start using u_log_context for debugging
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:51:00 +02:00
Nicolai Hähnle
ad33f2ddd8 radeonsi: re-order debug state dumping
Keep together the parts that won't use the deferred logging mechanism.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:57 +02:00
Nicolai Hähnle
40697e8678 radeonsi: make si_shader_selector_reference globally visible
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:55 +02:00
Nicolai Hähnle
4bbf6ded20 radeonsi: add reference count to si_compute
To allow keep-alive for deferred logging.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:53 +02:00
Nicolai Hähnle
bbaad18c04 radeonsi: implement pipe_context::set_log_context
We'll add radeonsi-specific code to set_log_context in later patches,
but we may want to log from common code. Hence keep the log pointer
in r600_common_context.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:48 +02:00
Nicolai Hähnle
81d7577d48 ddebug: add driver log to record dumps
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:44 +02:00
Nicolai Hähnle
1966d9ff41 gallium: add pipe_context::set_log_context
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:42 +02:00
Nicolai Hähnle
177144cefc util/log: add auto logger facility
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:40 +02:00
Nicolai Hähnle
1cc2fd57d1 util: add chunk logging module
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:31 +02:00
Aaron Watry
5e253fe338 clover/device: Calculate CL_DEVICE_MEM_BASE_ADDR_ALIGN in device
The CL CTS queries CL_DEVICE_MEM_BASE_ADDR_ALIGN for a device and
then allocates user pointers aligned to that value for its tests.

The minimum value is defined as:
  the size (in bits) of the largest OpenCL built-in data type supported
  by the device (long16 in FULL profile, long16 or int16 in EMBEDDED
  profile) for devices that are not of type CL_DEVICE_TYPE_CUSTOM.

At the moment, all known devices that support user pointers require
CPU page alignment for buffers created from user pointers, so just
query that from sysconf.

v3: Use std::max instead of MAX2 (Francisco)
    Add missing unistd include
v2: Use system page size instead of a new pipe cap

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by (v2): Jan Vesely <jan.vesely@rutgers.edu>
2017-08-21 20:21:52 -05:00
Brian Paul
4d2b21a326 svga: replace gotos with conditionals in array drawing code
No Piglit regressions.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-08-21 19:04:51 -06:00
Brian Paul
d50b8b91d7 llvmpipe: add some whitespace between functions in lp_texture.c
Trivial.
2017-08-21 19:04:51 -06:00
Brian Paul
196a0b28a0 svga: whitespace clean-up in svga_draw_private.h
Trivial.
2017-08-21 19:04:51 -06:00
Timothy Arceri
6fceace7bf gallium/docs: remove old llvmpipe TODO
Features are already covered by features.txt like all the other
drivers.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-08-22 11:03:08 +10:00
Marek Olšák
db039d67aa radeonsi: don't prefetch VBO descriptors if vertex elements == NULL
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-21 23:06:42 +02:00
Marek Olšák
ea1b97714d r600g: don't set up and don't call the fetch shader if there are no VS inputs 2017-08-21 23:06:42 +02:00
Rob Herring
4734bfc02a Android: Fix LLVM duplicated symbols linking for N and M
Both statically linking libLLVMCore and dynamically linking libLLVM causes
duplicated symbols in gallium_dri.so and it fails to dlopen. We don't
really need to link libLLVMCore, but just need generated headers to be
built first. Dynamically linking to libLLVM instead is enough to do
that. Thanks to Qiang Yu for finding the root cause.

With this change, we can align all versions and just have libLLVM as a
shared lib dependency.

This also requires changes in the M and N versions of LLVM to export the
include paths for libLLVM. AOSP master is okay.

Fixes: 26aee6f4d5 ("Android: rework LLVM build support")
Reported-by: Mauro Rossi <issor.oruam@gmail.com>
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2017-08-21 10:46:21 -05:00