Commit graph

62169 commits

Author SHA1 Message Date
Asahi Lina
025da70013 asahi: Add and support the no_fp16 driconf flag
This is the driconf equivalent of our debug no16 flag, which disables
fp16 support to work around apps using bad GLSL precision qualifiers.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Asahi Lina
45be01374f asahi: Add scaffolding for supporting driconf options
It's time to start using some of these, so add the required scaffolding
to be able to have driver-specific driconf handling for us.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Asahi Lina
4f793d878a asahi: Allocate staging resources as staging
We were never setting the flag, which made these resources
write-combine...

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
a58bb49fc0 asahi: Fixes for clang-warnings
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Karol Herbst
cce1933ca5 rusticl: enable asahi
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
b70172baff rusticl/memory: fallback if allocating linear images fails
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
7fd3e53279 asahi: handle images in is_format_supported
Some frontends differentiate between textures and images more explicitly
than st/mesa. So we might end up with PIPE_BIND_SHADER_IMAGE but not
PIPE_BIND_SAMPLER_VIEW in is_format_supported.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
3bc09aaf1a asahi: gracefully handle allocating linear images
Frontends might try to allocate linear textures or images, we  should
gracefully return NULL so frontends can do fallback paths.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
01aa487c40 asahi: implement clear_buffer
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
91f4062959 asahi: implement set_global_binding
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
9b59602338 asahi: implement get_compute_state_info
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
36e42299fa asahi: handle kernels
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
36235b5668 asahi: fetch available system memory
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Danylo Piliaiev
4dc75fc723 freedreno/fdl: Set LOSSLESSCOMPEN for image when ubwc is enabled on a7xx
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Lionel Landwerlin
40d7cb4000 intel/measure: track batch buffer sizes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
2023-09-05 11:50:02 +00:00
Dave Airlie
651c47f0ff llvmpipe/cs: further cleanups after tgsi removal.
These was still a few more places that could be polished better.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25045>
2023-09-05 07:14:27 +00:00
Mike Blumenkrantz
ca162bc82d zink: fix linear modifier dmabuf imports
these are disguised as INVALID modifiers, but really they're LINEAR

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25002>
2023-09-05 04:58:36 +00:00
Mike Blumenkrantz
977ef3b388 lavapipe: fix pipeline stride propagation
this is on the cso now

affects dEQP-VK.pipeline.fast_linked_library.extended_dynamic_state.before_good_static.large_stride

Fixes: 7672545223 ("gallium: move vertex stride to CSO")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24954>
2023-09-05 01:10:42 +00:00
Mike Blumenkrantz
f2865308c4 lavapipe: update vbo indices before propagating stride
the vbo index is used to set the stride, so it needs to be updated

affects dEQP-VK.pipeline.pipeline_library.bind_buffers_2.single.stride_0_4_offset_1_0.count_2

Fixes: 7672545223 ("gallium: move vertex stride to CSO")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24954>
2023-09-05 01:10:42 +00:00
Mike Blumenkrantz
4f7fb8341e zink: don't block reordering during ref updates in unordered blits
unordered blits handle all the reorder mechanics already, so any changes
here end up unnecessarily blocking further reordering

test case KHR-GLES3.packed_pixels.varied_rectangle.rgb

ref #9016

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24934>
2023-09-05 00:27:23 +00:00
Mike Blumenkrantz
98340dc8c4 zink: be more precise about flagging rp changes around unordered u_blitter
failing to update rp attachments as needed after unordered blits results in
broken (depth) rendering

Fixes: 3a9f7d7038 ("zink: implement unordered u_blitter calls")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24934>
2023-09-05 00:27:23 +00:00
Leo Liu
7876a2f685 radeonsi/vcn: fix the incorrect dt_size
Issue: For texture with multiple planes, the planes will point to the
same BO with the total size, so current vcn dt_size is incorrect.

(gdb) p/x *((struct si_resource *)(((struct vl_video_buffer *)out_surf)->resources[0]))
...
  buf = 0x5555558daa30,
  gpu_address = 0xffff800101000000,
  bo_size = 0xa2000,
...
}
(gdb) p/x *((struct si_resource *)(((struct vl_video_buffer *)out_surf)->resources[1]))
...
  buf = 0x5555558daa30,
  gpu_address = 0xffff800101000000,
  bo_size = 0xa2000,
...
}

This is because: in function static struct si_texture *si_texture_create_object(),
   if (plane0) {
      /* The buffer is shared with the first plane. */
      resource->bo_size = plane0->buffer.bo_size;
      ...
      radeon_bo_reference(sscreen->ws, &resource->buf, plane0->buffer.buf);
      resource->gpu_address = plane0->buffer.gpu_address;
   }

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9728
Cc: mesa-stable

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25013>
2023-09-04 22:04:58 +00:00
Tapani Pälli
0e9a26372b iris: implement Wa_14018912822
When MSAA is enabled, instead of using BLENDFACTOR_ZERO use CONST_COLOR,
CONST_ALPHA and supply zero by using blend constants.

We need info on blend state entries in the CSO so that we can set them
up properly.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24714>
2023-09-04 18:57:33 +00:00
Pavel Ondračka
58f1931104 r300: use w channel for scalar opcodes if possible
The opcodes write to w by default so using anything else means we can't
schedule anything in the rbg slot anyway becasue we have to replicate the
result from w. We already attempt to do this during the scheduling, but
at that point it is more tricky, so doing it early leads to much better
code. Performance++

RV530 benchmarks:

Lightsmark, 1280x800, fullscreen
before:
    N           Min           Max        Median           Avg        Stddev
x   5         27.32         27.36         27.34         27.34   0.015811388
after:
    N           Min           Max        Median           Avg        Stddev
x   5         27.53         27.61         27.59        27.576   0.034351128

Unigine Sanctuary, 1280x800, fullscreen, medium shaders
before:
    N           Min           Max        Median           Avg        Stddev
x   5       10.1211       10.1238       10.1214      10.12192  0.0011211601
after:
    N           Min           Max        Median           Avg        Stddev
x   5       10.4607       10.4637       10.4619      10.46206  0.0012441865

RV530 shader-db:
total instructions in shared programs: 129643 -> 128038 (-1.24%)
instructions in affected programs: 45415 -> 43810 (-3.53%)
helped: 514
HURT: 43
total presub in shared programs: 4912 -> 5201 (5.88%)
presub in affected programs: 752 -> 1041 (38.43%)
helped: 40
HURT: 30
total omod in shared programs: 381 -> 383 (0.52%)
omod in affected programs: 6 -> 8 (33.33%)
helped: 1
HURT: 3
total temps in shared programs: 16904 -> 16841 (-0.37%)
temps in affected programs: 1377 -> 1314 (-4.58%)
helped: 81
HURT: 52
total lits in shared programs: 3555 -> 3550 (-0.14%)
lits in affected programs: 294 -> 289 (-1.70%)
helped: 13
HURT: 11
total cycles in shared programs: 194771 -> 193734 (-0.53%)
cycles in affected programs: 79079 -> 78042 (-1.31%)
helped: 452
HURT: 84
GAINED: shaders/glamor/82.shader_test FS

RV370 shader-db:
total instructions in shared programs: 82116 -> 81600 (-0.63%)
instructions in affected programs: 11888 -> 11372 (-4.34%)
helped: 273
HURT: 40
total temps in shared programs: 12438 -> 12441 (0.02%)
temps in affected programs: 692 -> 695 (0.43%)
helped: 36
HURT: 39
total cycles in shared programs: 128140 -> 127630 (-0.40%)
cycles in affected programs: 25838 -> 25328 (-1.97%)
helped: 266
HURT: 41
GAINED: shaders/0ad/12.shader_test FS
GAINED: shaders/CC3-tiberium-wars/314.shader_test FS
GAINED: shaders/lightsmark/16.shader_test FS
GAINED: shaders/sanctuary/159.shader_test FS
GAINED: shaders/sanctuary/162.shader_test FS
GAINED: shaders/sanctuary/51.shader_test FS
GAINED: shaders/sanctuary/54.shader_test FS
GAINED: shaders/trine/fp-422.shader_test FS

Partial fix for: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6661

Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24889>
2023-09-04 16:13:43 +00:00
Carsten Haitzler
d01a60e8a3 kmsro: Add hdlcd DPU
Arm hdlcd display units do exist on Juno SoC's. This is the
first time Mesa has had to deal with panfrost working on these SoC's,
thus have to add hdlcd support.

Signed-off-by: Carsten Haitzler <carsten.haitzler@foss.arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25027>
2023-09-04 12:33:58 +00:00
Qiang Yu
b5eaec6c80 aco,radv,radeonsi: rename is_monolithic to merged_shader_compiled_separately
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24990>
2023-09-04 10:53:44 +08:00
Alexander Orzechowski
6b4d213a6f radeonsi: Set PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET for auxiliary contexts
This fixes a regression with context loss hardened compositors such as
wlroots or kwin where instead of continuing execution in a reset
situation, the process would be aborted. Although these applications set
their notification strategy to lose context on reset, radeonsi also
creates auxiliary contexts for its own use observed when
`egl_init_display` and `gbm_create_device` are called from these
compositors. Fix this by allowing a context loss on reset for these
auxiliary contexts.

Note: It seems this has been attempted before for another call site
creating auxiliary contexts, but this location was missed, hence the
fixed commit hash below.

Fixes: #9672
Fixes: 591aaea648

Signed-off-by: Alexander Orzechowski <alex@ozal.ski>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25023>
2023-09-04 01:09:03 +00:00
Aditya Swarup
fa6562b239 Revert "iris: Disable tiled memcpy for Tile4"
This reverts commit 0022a11ff4.

Enable path for Tile4 memcpy functions to be used.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
2023-09-02 21:49:05 -07:00
Rohan Garg
99a88ca4a2 crocus: fix GFX_VERx10 macro
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
2023-09-03 03:04:26 +00:00
Rohan Garg
802043018e crocus: add a __gen_get_batch_address declaration
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
2023-09-03 03:04:26 +00:00
Rohan Garg
50c2fe46fa iris: use the correct WA macros and lineage numbers
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0ce595a89a ("intel: use generated helpers for Wa_1508744258")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
2023-09-03 03:04:26 +00:00
Karol Herbst
f90f68aa1c rusticl/memory: only specify PIPE_BIND_SHADER_IMAGE where supported
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24982>
2023-09-02 10:11:24 +00:00
Jason Ekstrand
e956f6ad30 intel/isl: Allow Ys tiling
Ys & Yf are both implemented in ISL now, we still have some Yf issues
to investigate. Instead of disabling them in ISL, we disable them in
the two drivers.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Karol Herbst
5263802618 rusticl/memory: do not verify pitch for IMAGE1D_BUFFER
Devices might report an image_pitch_alignment of 0 leading to a division
by 0 trap.

Fixes: 06daa03c5c ("rusticl: Implement spec for cl_khr_image2d_from_buffer")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24993>
2023-09-01 20:06:30 +00:00
Eric Engestrom
a8c7a2fb69 ci/amd: split the polaris10 rules into one for each farm
There is now one polaris10 in each farm, so we need two rules for which
one to use.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24996>
2023-09-01 19:35:33 +00:00
Karol Herbst
46c17a8e54 rusticl/queue: properly implement clCreateCommandQueueWithProperties
It didn't do any of the error checking, but it was supposed to be. Also
the error checking was slightly wrong and we should return
CL_INVALID_QUEUE_PROPERTIES instead of CL_INVALID_VALUE for unsupported
properties.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24991>
2023-09-01 13:51:22 +00:00
Samuel Pitoiset
969f7b97fd zink/ci: add zink-radv-polaris10-valve
This introduces Zink/RADV testing on Polaris10!

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24976>
2023-09-01 12:52:42 +00:00
Qiang Yu
1f3858509c radeonsi: enable aco compile for part mode standalone vs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
2023-09-01 04:44:32 +00:00
Qiang Yu
287f7a9c35 radeonsi: set vs has prolog aco shader info
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
2023-09-01 04:44:32 +00:00
Qiang Yu
4247b742ec radeonsi: add vs prolog aco build
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
2023-09-01 04:44:32 +00:00
Qiang Yu
8c3b5ce0c4 radeonsi: fix aco options has_ls_vgpr_init_bug setup
Fixes: b313d950e2 ("radeonsi: enable aco compile for mono merged LS/HS")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
2023-09-01 04:44:32 +00:00
Qiang Yu
ec57236824 radeonsi: extract si_get_vs_prolog_args to be shared with aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
2023-09-01 04:44:32 +00:00
Qiang Yu
07b62af810 radeonsi: remove is_monolithic from vs prolog key
We do not generate vs prolog for monolithic shader any more.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
2023-09-01 04:44:32 +00:00
Qiang Yu
4c10bf1e6d radeonsi: fill aco_shader_info->is_monolithic
Fixes: 80177e0296 ("aco: add support for compiling VS+TCS separately on GFX9+")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24944>
2023-09-01 03:06:03 +00:00
Karol Herbst
667375999c rusticl/event: disable profiling for devices without timestamps
Timestamp queries are strictly required, but a bit odd to not expose CL
for not supporting it...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24938>
2023-09-01 02:48:55 +00:00
Karol Herbst
8e4d51aa1f rusticl/query: fix use-after-free, but also fix incorrect usage of unsafe
`PipeQuery::new` create a `PipeQuery` wrapper before handling errors, so
we ended up calling `drop` and destroy_query, meaning the latter ended up
being called twice.

While at it, also restrict visibility of related methods and add some
unsafe declarations.

Fixes: 52e53938c3 ("rusticl: Wrap pipe queries")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24938>
2023-09-01 02:48:55 +00:00
Lang Yu
f2c8cb2649 radeonsi: use wave size to determine index stride
Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24920>
2023-08-31 20:30:03 +00:00
Lang Yu
42abb231aa radeonsi: use AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32 to determine wave size
Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24920>
2023-08-31 20:30:03 +00:00
Karol Herbst
1a20ac7891 rusticl/disk_cache: fix stack corruption
The length passed to mesa_bytes_to_hex is the one of the input, not output
data.

Fixes: fbe9a7ca3e ("rusticl/mesa: create proper build-id hash for the disk cache")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24967>
2023-08-31 15:17:50 +00:00
Lionel Landwerlin
bcc0ec8e6c anv: enable KHR_maintenance5
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24387>
2023-08-31 16:02:52 +03:00