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796 commits

Author SHA1 Message Date
Jason Ekstrand
8c2b9d1529 anv/bo_pool: Allow freeing BOs where the anv_bo is in the BO itself 2016-03-07 22:23:44 -08:00
Nanley Chery
181b142fbd anv/device: Up device limits for 3D and array texture dimensions 
The limit for these textures is 2048 not 1024.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
 2016-03-07 15:21:50 -08:00
Jason Ekstrand
428ffc9c13 anv/device: Actually free the CPU-side fence struct again 
In 23de78768, when we switched from allocating individual BOs to using the
pool for fences, we accidentally deleted the free.
 2016-03-07 14:50:52 -08:00
Kristian Høgsberg Kristensen
32aa01663f anv: Quiet pTessellationState warning 
Some application pass a dummy for pTessellationState which results in a
lot of noise. Only warn if we're actually given tessellation shadear
stages.
 2016-03-06 22:06:24 -08:00
Jason Ekstrand
23de78768b anv: Create fences from the batch BO pool 
Applications may create a *lot* of fences, perhaps as much as one per
vkQueueSubmit.  Really, they're supposed to use ResetFence, but it's easy
enough for us to make them crazy-cheap so we might as well.
 2016-03-06 14:26:52 -08:00
Jason Ekstrand
21ee5fd326 anv: Emit null render targets 
v2 (Francisco Jerez): Add the state_offset to the surface state offset
 2016-03-05 20:47:10 -08:00
Jason Ekstrand
8502794c12 anv/pipeline: Handle null wm_prog_data in 3DSTATE_CLIP 2016-03-05 14:42:16 -08:00
Kristian Høgsberg Kristensen
7b348ab8a0 anv: Fix rebase error 2016-03-05 14:33:50 -08:00
Kristian Høgsberg Kristensen
34326f46df anv: Turn pipeline cache on by default 
Move the environment variable check to cache creation time so we block
both lookups and uploads if it's turned off.
 2016-03-05 13:54:24 -08:00
Kristian Høgsberg Kristensen
f2b37132cb anv: Check if shader if present before uploading to cache 
Between the initial check the returns NO_KERNEL and compiling the
shader, other threads may have added the shader to the cache. Before
uploading the kernel, check again (under the mutex) that the compiled
shader still isn't present.
 2016-03-05 13:54:24 -08:00
Kristian Høgsberg Kristensen
30bbe28b7e anv: Always use point size from the shader 
There is no API for setting the point size and the shader is always
required to set it. Section 24.4:

   "If the value written to PointSize is less than or equal to zero, or
    if no value was written to PointSize, results are undefined."

As such, we can just always program PointWidthSource to Vertex. This
simplifies anv_pipeline a bit and avoids trouble when we enable the
pipeline cache and don't have writes_point_size in the prog_data.
 2016-03-05 13:54:24 -08:00
Kristian Høgsberg Kristensen
6139fe9a77 anv: Also cache the struct anv_pipeline_binding maps 
This is state the we generate when compiling the shaders and we need it
for mapping resources from descriptor sets to binding table indices.
 2016-03-05 13:50:07 -08:00
Kristian Høgsberg Kristensen
584f39c65e anv: Don't re-upload shaders when merging 
Using anv_pipeline_cache_upload_kernel() will re-upload the kernel and
prog_data when we merge caches. Since the kernel and prog_data is
already in the program_stream, use anv_pipeline_cache_add_entry()
instead to only add the entry to the hash table.
 2016-03-05 13:50:07 -08:00
Kristian Høgsberg Kristensen
626559ed37 anv: Add anv_pipeline_cache_add_entry() 
This function will grow the cache to make room and then add the entry.
 2016-03-05 13:50:07 -08:00
Kristian Høgsberg Kristensen
07441c344c anv: Rename anv_pipeline_cache_add_entry() to 'set' 
This function is a helper that unconditionally sets a hash table entry
and expects the cache to have enough room. Calling it 'add_entry'
suggests it will grow the cache as needed.
 2016-03-05 13:50:07 -08:00
Kristian Høgsberg Kristensen
87967a2c85 anv: Simplify pipeline cache control flow a bit 
No functional change, but the control flow around searching the cache
and falling back to compiling is a bit simpler.
 2016-03-05 13:50:07 -08:00
Kristian Høgsberg Kristensen
2b29342fae anv: Store prog data in pipeline cache stream 
We have to keep it there for the cache to work, so let's not have an
extra copy in struct anv_pipeline too.
 2016-03-05 13:50:07 -08:00
Kristian Høgsberg Kristensen
37c5e70253 anv: Rename 'table' to 'hash_table' in anv_pipeline_cache 
A little less ambiguous.
 2016-03-05 13:50:07 -08:00
Kristian Høgsberg Kristensen
c028ffea70 anv: Serialize as much pipeline cache as we can 
We can serialize as much as the application asks for and just stop once
we run out of memory. This lets applications use a fixed amount of
space for caching and still get some benefit.
 2016-03-05 13:50:07 -08:00
Kristian Høgsberg Kristensen
cd812f086e anv: Use 1.0 pipeline cache header 
The final version of the pipeline cache header adds a few more fields.
 2016-03-05 13:50:07 -08:00
Kristian Høgsberg Kristensen
26ed943eb9 anv: Fix shader key hashing 
This was copied from inline code to a helper and wasn't updated to hash
a pointer instead.
 2016-03-05 13:50:07 -08:00
Kristian Høgsberg Kristensen
3baf8af947 anv: Remove excess whitespace 2016-03-05 13:50:07 -08:00
Kristian Høgsberg Kristensen
ab36eae5e7 anv: Remove left-over bits of sparse-descriptor code 2016-03-05 13:50:07 -08:00
Jason Ekstrand
1afdfc3e6e anv/pipeline: Implement the depth compare EQUAL workaround on gen8+ 2016-03-05 09:59:28 -08:00
Jason Ekstrand
7c1660aa14 anv: Don't allow D16_UNORM to be combined with stencil 
Among other things, this can cause the depth or stencil test to spurriously
fail when the fragment shader uses discard.
 2016-03-05 09:59:28 -08:00
Jason Ekstrand
9a90176d48 anv/pipeline: Calculate the correct max_source_attr for 3DSTATE_SBE 2016-03-05 09:59:28 -08:00
Jordan Justen
81f30e2f50 anv/hsw: Move query code to genX file for Haswell 
This fixes many CTS cases, but will require an update to the kernel
command parser register whitelist. (The CS GPRs and TIMESTAMP
registers need to be whitelisted.)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2016-03-05 01:08:07 -08:00
Nanley Chery
4e75f9b219 anv: Implement VK_REMAINING_{MIP_LEVELS,ARRAY_LAYERS} 
v2: Subtract the baseMipLevel and baseArrayLayer (Jason)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
 2016-03-04 21:25:23 -08:00
Jason Ekstrand
c1436e80ef anv/meta_clear: Set the right number of dynamic states 2016-03-04 19:18:20 -08:00
Jason Ekstrand
cc57efc67a anv/pipeline: Fix depthBiasEnable on gen7 
The first time I tried to fix this, I set the wrong fields.
 2016-03-04 17:56:12 -08:00
Jason Ekstrand
653261285e anv/cmd_buffer: Reset the state streams when resetting the command buffer 2016-03-04 17:54:29 -08:00
Jason Ekstrand
f700d16a89 anv/cmd_buffer: Include Haswell in set_subpass 2016-03-04 17:54:29 -08:00
Nanley Chery
a6fb62a864 isl: Fix RenderTargetViewExtent for mipmapped 3D surfaces 
Match the comment stated above the assignment.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
 2016-03-04 13:20:44 -08:00
Nanley Chery
b80c8ebc45 isl: Get rid of isl_surf_fill_state_info::level0_extent_px 
This field is no longer needed.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
 2016-03-04 13:20:03 -08:00
Jason Ekstrand
d154a5ebd6 anv/cmd_buffer: Let the pipeline set StencilBufferWriteEnable on gen9 2016-03-04 12:23:01 -08:00
Jason Ekstrand
f374765ce6 anv/cmd_buffer: Mask stencil reference values 2016-03-04 12:22:32 -08:00
Jason Ekstrand
d61dcec64d anv/clear: Pull the stencil write mask from the pipeline 
The stencil write mask wasn't getting set at all so we were using whatever
write mask happend to be left over by the application.
 2016-03-04 12:03:00 -08:00
Jason Ekstrand
ec18fef88d anv/pipeline: Set StencilBufferWriteEnable from the pipeline 
The hardware docs say that StencilBufferWriteEnable should only be set if
StencilTestEnable is set.  It seems reasonable to set them together.
 2016-03-04 12:03:00 -08:00
Jason Ekstrand
fcd8e57185 anv/pipeline: More competent gen8 clipping 2016-03-04 12:03:00 -08:00
Jason Ekstrand
a8afd29653 anv/pipeline: Use the right provoking vertex for triangle fans 2016-03-04 12:03:00 -08:00
Jason Ekstrand
fa8539dd6b anv/pipeline: Respect pRasterizationState->depthBiasEnable 2016-03-04 12:03:00 -08:00
Kenneth Graunke
9d7faadd8a anv: Fix backwards shadow comparisons 
sample_c is backwards from what GL and Vulkan expect.

See intel_state.c in i965.

v2: Drop unused vk_to_gen_compare_op.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
 2016-03-04 11:35:46 -08:00
Kenneth Graunke
3ed260f54c hack to make dota 2 menus work 2016-03-03 16:21:09 -08:00
Jason Ekstrand
56ba13c994 isl/surface_state: Set L2 bypass disable for certain BC* formats 2016-03-03 16:16:57 -08:00
Kenneth Graunke
623ce595a9 anv: Compile shader stages in pipeline order. 
Instead of the arbitrary order modules might be specified in.

Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
 2016-03-03 11:36:19 -08:00
Nanley Chery
8dddc3fb1e anv/meta: Delete unused functions 
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
 2016-03-03 11:26:44 -08:00
Nanley Chery
d20f6abc85 anv/meta: Use blitter API for state-handling in Buffer Update/Copy 
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
 2016-03-03 11:26:42 -08:00
Nanley Chery
318b67d157 anv/meta: Use blitter API in do_buffer_copy() 
v2: Keep pitch in units of bytes (Jason)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
 2016-03-03 11:26:36 -08:00
Nanley Chery
96ff4d0679 anv/meta: Use blitter API in anv_CmdCopyImage() 
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
 2016-03-03 11:26:35 -08:00
Nanley Chery
9b6c95d46e anv/meta: Use blitter API for copies between Images and Buffers 
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
 2016-03-03 11:25:20 -08:00