From fff585bdb80b83d754aaa61bf5306268a7da5e06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 10 Jun 2023 21:41:49 -0400 Subject: [PATCH] radeonsi: don't do BREAK_BATCH for context regs with only 1 context per batch because it has no effect Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_state.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 8075ec1c57a..44a5558bbce 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -72,7 +72,8 @@ static void si_emit_cb_render_state(struct si_context *sctx) /* GFX9: Flush DFSM when CB_TARGET_MASK changes. * I think we don't have to do anything between IBs. */ - if (sctx->screen->dpbb_allowed && sctx->last_cb_target_mask != cb_target_mask) { + if (sctx->screen->dpbb_allowed && sctx->last_cb_target_mask != cb_target_mask && + sctx->screen->pbb_context_states_per_bin > 1) { sctx->last_cb_target_mask = cb_target_mask; radeon_begin(cs); @@ -3550,7 +3551,8 @@ static void si_emit_framebuffer_state(struct si_context *sctx) radeon_set_context_reg(R_028208_PA_SC_WINDOW_SCISSOR_BR, S_028208_BR_X(state->width) | S_028208_BR_Y(state->height)); - if (sctx->screen->dpbb_allowed) { + if (sctx->screen->dpbb_allowed && + sctx->screen->pbb_context_states_per_bin > 1) { radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); }