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radv/gfx10: update OVERWRITE_COMBINER_{MRT_SHARING,WATERMARK}

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DCC related, mirror RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com
This commit is contained in:
Samuel Pitoiset 2019-07-11 15:51:40 +02:00
parent c6fa4de15d
commit ffd6a979bf
1 changed files with 4 additions and 16 deletions
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20
src/amd/vulkan/radv_cmd_buffer.c
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@ -1857,7 +1857,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
int i; int i;
struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer; struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass; const struct radv_subpass *subpass = cmd_buffer->state.subpass;
unsigned num_bpp64_colorbufs = 0;
/* this may happen for inherited secondary recording */ /* this may happen for inherited secondary recording */
if (!framebuffer) if (!framebuffer)
@ -1873,7 +1872,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
int idx = subpass->color_attachments[i].attachment; int idx = subpass->color_attachments[i].attachment;
struct radv_attachment_info *att = &framebuffer->attachments[idx]; struct radv_attachment_info *att = &framebuffer->attachments[idx];
struct radv_image_view *iview = att->attachment; struct radv_image_view *iview = att->attachment;
struct radv_image *image = iview->image;
VkImageLayout layout = subpass->color_attachments[i].layout; VkImageLayout layout = subpass->color_attachments[i].layout;
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo); radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
@ -1883,9 +1881,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout); radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
radv_load_color_clear_metadata(cmd_buffer, iview, i); radv_load_color_clear_metadata(cmd_buffer, iview, i);
if (image->planes[0].surface.bpe >= 8)
num_bpp64_colorbufs++;
} }
if (subpass->depth_stencil_attachment) { if (subpass->depth_stencil_attachment) {
@ -1924,19 +1919,12 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) { if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
bool disable_constant_encode = bool disable_constant_encode =
cmd_buffer->device->physical_device->has_dcc_constant_encode; cmd_buffer->device->physical_device->has_dcc_constant_encode;
uint8_t watermark = 4; /* Default value for GFX8. */ enum chip_class chip_class =
cmd_buffer->device->physical_device->rad_info.chip_class;
/* For optimal DCC performance. */ uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
if (num_bpp64_colorbufs >= 5) {
watermark = 8;
} else {
watermark = 6;
}
}
radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL, radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) | S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) | S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode)); S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
} }