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radeonsi: Use vcn version instead of CHIP family for VCNs

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Decouple it from CHIP family, based on HW query infomation.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22904>
This commit is contained in:
Leo Liu 2023-05-01 11:50:51 -04:00 • committed by Marge Bot
parent 09e59553ec
commit ffbbf23ef8
7 changed files with 76 additions and 104 deletions
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3
src/amd/common/ac_gpu_info.c
View file

@ -1684,8 +1684,7 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
[AMD_IP_VCE] = "VCE", [AMD_IP_VCE] = "VCE",
[AMD_IP_UVD_ENC] = "UVD_ENC", [AMD_IP_UVD_ENC] = "UVD_ENC",
[AMD_IP_VCN_DEC] = "VCN_DEC", [AMD_IP_VCN_DEC] = "VCN_DEC",
[AMD_IP_VCN_ENC] = (info->family >= CHIP_GFX1100 || [AMD_IP_VCN_ENC] = (info->vcn_ip_version >= VCN_4_0_0) ? "VCN" : "VCN_ENC",
info->family == CHIP_GFX940) ? "VCN" : "VCN_ENC",
[AMD_IP_VCN_JPEG] = "VCN_JPG", [AMD_IP_VCN_JPEG] = "VCN_JPG",
}; };

65
src/gallium/drivers/radeonsi/radeon_vcn_dec.c
View file

@ -2107,7 +2107,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
/* default probability + probability data */ /* default probability + probability data */
ctx_size = 2304 * 5; ctx_size = 2304 * 5;
if (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR) { if (((struct si_screen *)dec->screen)->info.vcn_ip_version >= VCN_2_0_0) {
/* SRE collocated context data */ /* SRE collocated context data */
ctx_size += 32 * 2 * 128 * 68; ctx_size += 32 * 2 * 128 * 68;
/* SMP collocated context data */ /* SMP collocated context data */
@ -2180,8 +2180,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE; decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
decode->db_pitch = align(dec->base.width, dec->db_alignment); decode->db_pitch = align(dec->base.width, dec->db_alignment);
if ((((struct si_screen*)dec->screen)->info.family >= CHIP_NAVI21 || if ((((struct si_screen*)dec->screen)->info.vcn_ip_version >= VCN_3_0_0) &&
((struct si_screen*)dec->screen)->info.family == CHIP_GFX940) &&
(dec->stream_type == RDECODE_CODEC_VP9 || dec->stream_type == RDECODE_CODEC_AV1 || (dec->stream_type == RDECODE_CODEC_VP9 || dec->stream_type == RDECODE_CODEC_AV1 ||
dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10))
decode->db_aligned_height = align(dec->base.height, 64); decode->db_aligned_height = align(dec->base.height, 64);
@ -2733,7 +2732,7 @@ static unsigned calc_dpb_size(struct radeon_decoder *dec)
max_references = MAX2(max_references, 9); max_references = MAX2(max_references, 9);
if (dec->dpb_type == DPB_MAX_RES) if (dec->dpb_type == DPB_MAX_RES)
dpb_size = (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR) dpb_size = (((struct si_screen *)dec->screen)->info.vcn_ip_version >= VCN_2_0_0)
? (8192 * 4320 * 3 / 2) * max_references ? (8192 * 4320 * 3 / 2) * max_references
: (4096 * 3000 * 3 / 2) * max_references; : (4096 * 3000 * 3 / 2) * max_references;
else else
@ -3078,7 +3077,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
dec->ws = ws; dec->ws = ws;
if (u_reduce_video_profile(templ->profile) != PIPE_VIDEO_FORMAT_JPEG && if (u_reduce_video_profile(templ->profile) != PIPE_VIDEO_FORMAT_JPEG &&
(sctx->gfx_level >= GFX11 || sctx->family == CHIP_GFX940)) { (sctx->vcn_ip_ver >= VCN_4_0_0)) {
dec->vcn_dec_sw_ring = true; dec->vcn_dec_sw_ring = true;
ring = AMD_IP_VCN_UNIFIED; ring = AMD_IP_VCN_UNIFIED;
} }
@ -3093,9 +3092,9 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
if (dec->stream_type == RDECODE_CODEC_JPEG) { if (dec->stream_type == RDECODE_CODEC_JPEG) {
if (sctx->family == CHIP_MI100 || sctx->family == CHIP_MI200) if (sctx->vcn_ip_ver == VCN_2_5_0 || sctx->vcn_ip_ver == VCN_2_6_0)
dec->njctx = 2; dec->njctx = 2;
else if (sctx->family == CHIP_GFX940) else if (sctx->vcn_ip_ver == VCN_4_0_3)
dec->njctx = 24; dec->njctx = 24;
else else
dec->njctx = 1; dec->njctx = 1;
@ -3122,8 +3121,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
for (i = 0; i < ARRAY_SIZE(dec->render_pic_list); i++) for (i = 0; i < ARRAY_SIZE(dec->render_pic_list); i++)
dec->render_pic_list[i] = NULL; dec->render_pic_list[i] = NULL;
if ((sctx->family >= CHIP_NAVI21 || sctx->family == CHIP_GFX940) && if ((sctx->vcn_ip_ver >= VCN_3_0_0) && (stream_type == RDECODE_CODEC_H264_PERF)) {
(stream_type == RDECODE_CODEC_H264_PERF)) {
for (i = 0; i < ARRAY_SIZE(dec->h264_valid_ref_num); i++) for (i = 0; i < ARRAY_SIZE(dec->h264_valid_ref_num); i++)
dec->h264_valid_ref_num[i] = (unsigned) -1; dec->h264_valid_ref_num[i] = (unsigned) -1;
for (i = 0; i < ARRAY_SIZE(dec->h264_valid_poc_num); i++) for (i = 0; i < ARRAY_SIZE(dec->h264_valid_poc_num); i++)
@ -3169,18 +3167,18 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
} }
} }
if ((sctx->family >= CHIP_NAVI21 || sctx->family == CHIP_GFX940) && if ((sctx->vcn_ip_ver >= VCN_3_0_0) &&
(stream_type == RDECODE_CODEC_VP9 || (stream_type == RDECODE_CODEC_VP9 ||
stream_type == RDECODE_CODEC_AV1 || stream_type == RDECODE_CODEC_AV1 ||
((stream_type == RDECODE_CODEC_H265) && templ->expect_chunked_decode) || ((stream_type == RDECODE_CODEC_H265) && templ->expect_chunked_decode) ||
((stream_type == RDECODE_CODEC_H264_PERF) && templ->expect_chunked_decode))) ((stream_type == RDECODE_CODEC_H264_PERF) && templ->expect_chunked_decode)))
dec->dpb_type = DPB_DYNAMIC_TIER_2; dec->dpb_type = DPB_DYNAMIC_TIER_2;
else if (sctx->family <= CHIP_NAVI14 && stream_type == RDECODE_CODEC_VP9) else if (sctx->vcn_ip_ver <= VCN_2_6_0 && stream_type == RDECODE_CODEC_VP9)
dec->dpb_type = DPB_DYNAMIC_TIER_1; dec->dpb_type = DPB_DYNAMIC_TIER_1;
else else
dec->dpb_type = DPB_MAX_RES; dec->dpb_type = DPB_MAX_RES;
dec->db_alignment = (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR && dec->db_alignment = (((struct si_screen *)dec->screen)->info.vcn_ip_version >= VCN_2_0_0 &&
dec->base.width > 32 && (dec->stream_type == RDECODE_CODEC_VP9 || dec->base.width > 32 && (dec->stream_type == RDECODE_CODEC_VP9 ||
dec->stream_type == RDECODE_CODEC_AV1 || dec->stream_type == RDECODE_CODEC_AV1 ||
dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) ? 64 : 32; dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) ? 64 : 32;
@ -3197,50 +3195,47 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
dec->addr_gfx_mode = RDECODE_ARRAY_MODE_LINEAR; dec->addr_gfx_mode = RDECODE_ARRAY_MODE_LINEAR;
dec->av1_version = RDECODE_AV1_VER_0; dec->av1_version = RDECODE_AV1_VER_0;
switch (sctx->family) { switch (sctx->vcn_ip_ver) {
case CHIP_RAVEN: case VCN_1_0_0:
case CHIP_RAVEN2: case VCN_1_0_1:
dec->reg.data0 = RDECODE_VCN1_GPCOM_VCPU_DATA0; dec->reg.data0 = RDECODE_VCN1_GPCOM_VCPU_DATA0;
dec->reg.data1 = RDECODE_VCN1_GPCOM_VCPU_DATA1; dec->reg.data1 = RDECODE_VCN1_GPCOM_VCPU_DATA1;
dec->reg.cmd = RDECODE_VCN1_GPCOM_VCPU_CMD; dec->reg.cmd = RDECODE_VCN1_GPCOM_VCPU_CMD;
dec->reg.cntl = RDECODE_VCN1_ENGINE_CNTL; dec->reg.cntl = RDECODE_VCN1_ENGINE_CNTL;
dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V1; dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V1;
break; break;
case CHIP_NAVI10: case VCN_2_0_0:
case CHIP_NAVI12: case VCN_2_0_2:
case CHIP_NAVI14: case VCN_2_0_3:
case CHIP_RENOIR: case VCN_2_2_0:
dec->reg.data0 = RDECODE_VCN2_GPCOM_VCPU_DATA0; dec->reg.data0 = RDECODE_VCN2_GPCOM_VCPU_DATA0;
dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1; dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD; dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;
dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL; dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V2; dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V2;
break; break;
case CHIP_MI100: case VCN_2_5_0:
case CHIP_MI200: case VCN_2_6_0:
case CHIP_NAVI21: case VCN_3_0_0:
case CHIP_NAVI22: case VCN_3_0_2:
case CHIP_NAVI23: case VCN_3_0_16:
case CHIP_NAVI24: case VCN_3_0_33:
case CHIP_VANGOGH: case VCN_3_1_1:
case CHIP_REMBRANDT: case VCN_3_1_2:
case CHIP_RAPHAEL_MENDOCINO:
dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0; dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1; dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD; dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL; dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V2; dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V2;
break; break;
case CHIP_GFX940: case VCN_4_0_3:
dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V3; dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V3;
dec->addr_gfx_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX9; dec->addr_gfx_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX9;
dec->av1_version = RDECODE_AV1_VER_1; dec->av1_version = RDECODE_AV1_VER_1;
break; break;
case CHIP_GFX1100: case VCN_4_0_0:
case CHIP_GFX1101: case VCN_4_0_2:
case CHIP_GFX1102: case VCN_4_0_4:
case CHIP_GFX1103_R1:
case CHIP_GFX1103_R2:
dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V2; dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V2;
dec->addr_gfx_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11; dec->addr_gfx_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11;
dec->av1_version = RDECODE_AV1_VER_1; dec->av1_version = RDECODE_AV1_VER_1;
@ -3317,7 +3312,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
list_inithead(&dec->dpb_unref_list); list_inithead(&dec->dpb_unref_list);
} }
dec->tmz_ctx = sctx->family < CHIP_RENOIR; dec->tmz_ctx = sctx->vcn_ip_ver <= VCN_2_2_0 && sctx->vcn_ip_ver != VCN_UNKNOWN;
return &dec->base; return &dec->base;

6
src/gallium/drivers/radeonsi/radeon_vcn_enc.c
View file

@ -992,11 +992,11 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
goto error; goto error;
} }
if (sscreen->info.gfx_level >= GFX11) if (sscreen->info.vcn_ip_version >= VCN_4_0_0)
radeon_enc_4_0_init(enc); radeon_enc_4_0_init(enc);
else if (sscreen->info.family >= CHIP_NAVI21) else if (sscreen->info.vcn_ip_version >= VCN_3_0_0)
radeon_enc_3_0_init(enc); radeon_enc_3_0_init(enc);
else if (sscreen->info.family >= CHIP_RENOIR) else if (sscreen->info.vcn_ip_version >= VCN_2_0_0)
radeon_enc_2_0_init(enc); radeon_enc_2_0_init(enc);
else else
radeon_enc_1_2_init(enc); radeon_enc_1_2_init(enc);

98
src/gallium/drivers/radeonsi/si_get.c
View file

@ -589,7 +589,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
sscreen->info.ip[AMD_IP_VCN_ENC].num_queues)) sscreen->info.ip[AMD_IP_VCN_ENC].num_queues))
return 0; return 0;
if (sscreen->info.family == CHIP_GFX940) if (sscreen->info.vcn_ip_version == VCN_4_0_3)
return 0; return 0;
switch (param) { switch (param) {
@ -598,11 +598,12 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
/* in case it is explicitly marked as not supported by the kernel */ /* in case it is explicitly marked as not supported by the kernel */
(QUERYABLE_KERNEL ? KERNEL_ENC_CAP(codec, valid) : 1) && (QUERYABLE_KERNEL ? KERNEL_ENC_CAP(codec, valid) : 1) &&
((codec == PIPE_VIDEO_FORMAT_MPEG4_AVC && ((codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
(sscreen->info.family >= CHIP_RAVEN || si_vce_is_fw_version_supported(sscreen))) || (sscreen->info.vcn_ip_version >= VCN_1_0_0 || si_vce_is_fw_version_supported(sscreen))) ||
(profile == PIPE_VIDEO_PROFILE_HEVC_MAIN && (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
(sscreen->info.family >= CHIP_RAVEN || si_radeon_uvd_enc_supported(sscreen))) || (sscreen->info.vcn_ip_version >= VCN_1_0_0 || si_radeon_uvd_enc_supported(sscreen))) ||
(profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 && sscreen->info.family >= CHIP_RENOIR) || (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 && sscreen->info.vcn_ip_version >= VCN_2_0_0) ||
(profile == PIPE_VIDEO_PROFILE_AV1_MAIN && (sscreen->info.family >= CHIP_GFX1100)))); (profile == PIPE_VIDEO_PROFILE_AV1_MAIN &&
(sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3))));
case PIPE_VIDEO_CAP_NPOT_TEXTURES: case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1; return 1;
case PIPE_VIDEO_CAP_MIN_WIDTH: case PIPE_VIDEO_CAP_MIN_WIDTH:
@ -633,21 +634,15 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
case PIPE_VIDEO_CAP_STACKED_FRAMES: case PIPE_VIDEO_CAP_STACKED_FRAMES:
return (sscreen->info.family < CHIP_TONGA) ? 1 : 2; return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
case PIPE_VIDEO_CAP_MAX_TEMPORAL_LAYERS: case PIPE_VIDEO_CAP_MAX_TEMPORAL_LAYERS:
if (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC && return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
sscreen->info.family >= CHIP_RAVEN) sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 4 : 0;
return 4;
else
return 0;
case PIPE_VIDEO_CAP_ENC_QUALITY_LEVEL: case PIPE_VIDEO_CAP_ENC_QUALITY_LEVEL:
if (sscreen->info.family >= CHIP_RAVEN) return (sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 32 : 0;
return 32;
else
return 0;
case PIPE_VIDEO_CAP_ENC_SUPPORTS_MAX_FRAME_SIZE: case PIPE_VIDEO_CAP_ENC_SUPPORTS_MAX_FRAME_SIZE:
return (sscreen->info.family >= CHIP_RAVEN) ? 1 : 0; return (sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 1 : 0;
case PIPE_VIDEO_CAP_ENC_HEVC_FEATURE_FLAGS: case PIPE_VIDEO_CAP_ENC_HEVC_FEATURE_FLAGS:
if ((sscreen->info.family >= CHIP_RAVEN) && if ((sscreen->info.vcn_ip_version >= VCN_1_0_0) &&
(profile == PIPE_VIDEO_PROFILE_HEVC_MAIN || (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) { profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) {
union pipe_h265_enc_cap_features pipe_features; union pipe_h265_enc_cap_features pipe_features;
@ -658,7 +653,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
pipe_features.bits.constrained_intra_pred = PIPE_ENC_FEATURE_SUPPORTED; pipe_features.bits.constrained_intra_pred = PIPE_ENC_FEATURE_SUPPORTED;
pipe_features.bits.deblocking_filter_disable pipe_features.bits.deblocking_filter_disable
= PIPE_ENC_FEATURE_SUPPORTED; = PIPE_ENC_FEATURE_SUPPORTED;
if (sscreen->info.family >= CHIP_RENOIR) if (sscreen->info.vcn_ip_version >= VCN_2_0_0)
pipe_features.bits.sao = PIPE_ENC_FEATURE_SUPPORTED; pipe_features.bits.sao = PIPE_ENC_FEATURE_SUPPORTED;
return pipe_features.value; return pipe_features.value;
@ -666,7 +661,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
return 0; return 0;
case PIPE_VIDEO_CAP_ENC_HEVC_BLOCK_SIZES: case PIPE_VIDEO_CAP_ENC_HEVC_BLOCK_SIZES:
if (sscreen->info.family >= CHIP_RAVEN && if (sscreen->info.vcn_ip_version >= VCN_1_0_0 &&
(profile == PIPE_VIDEO_PROFILE_HEVC_MAIN || (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) { profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) {
union pipe_h265_enc_cap_block_sizes pipe_block_sizes; union pipe_h265_enc_cap_block_sizes pipe_block_sizes;
@ -683,16 +678,13 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
return 0; return 0;
case PIPE_VIDEO_CAP_ENC_SUPPORTS_ASYNC_OPERATION: case PIPE_VIDEO_CAP_ENC_SUPPORTS_ASYNC_OPERATION:
return (sscreen->info.family >= CHIP_RAVEN) ? 1 : 0; return (sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 1 : 0;
case PIPE_VIDEO_CAP_ENC_MAX_SLICES_PER_FRAME: case PIPE_VIDEO_CAP_ENC_MAX_SLICES_PER_FRAME:
if (sscreen->info.family >= CHIP_RAVEN) return (sscreen->info.vcn_ip_version >= VCN_1_0_0) ? 128 : 1;
return 128;
else
return 1;
case PIPE_VIDEO_CAP_ENC_SLICES_STRUCTURE: case PIPE_VIDEO_CAP_ENC_SLICES_STRUCTURE:
if (sscreen->info.family >= CHIP_RENOIR) { if (sscreen->info.vcn_ip_version >= VCN_2_0_0) {
int value = (PIPE_VIDEO_CAP_SLICE_STRUCTURE_POWER_OF_TWO_ROWS | int value = (PIPE_VIDEO_CAP_SLICE_STRUCTURE_POWER_OF_TWO_ROWS |
PIPE_VIDEO_CAP_SLICE_STRUCTURE_EQUAL_ROWS | PIPE_VIDEO_CAP_SLICE_STRUCTURE_EQUAL_ROWS |
PIPE_VIDEO_CAP_SLICE_STRUCTURE_EQUAL_MULTI_ROWS); PIPE_VIDEO_CAP_SLICE_STRUCTURE_EQUAL_MULTI_ROWS);
@ -701,7 +693,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
return 0; return 0;
case PIPE_VIDEO_CAP_ENC_AV1_FEATURE: case PIPE_VIDEO_CAP_ENC_AV1_FEATURE:
if (sscreen->info.family >= CHIP_GFX1100) { if (sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3) {
union pipe_av1_enc_cap_features attrib; union pipe_av1_enc_cap_features attrib;
attrib.value = 0; attrib.value = 0;
@ -725,7 +717,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
return 0; return 0;
case PIPE_VIDEO_CAP_ENC_AV1_FEATURE_EXT1: case PIPE_VIDEO_CAP_ENC_AV1_FEATURE_EXT1:
if (sscreen->info.family >= CHIP_GFX1100) { if (sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3) {
union pipe_av1_enc_cap_features_ext1 attrib_ext1; union pipe_av1_enc_cap_features_ext1 attrib_ext1;
attrib_ext1.value = 0; attrib_ext1.value = 0;
attrib_ext1.bits.interpolation_filter = PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_EIGHT_TAP | attrib_ext1.bits.interpolation_filter = PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_EIGHT_TAP |
@ -741,7 +733,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
return 0; return 0;
case PIPE_VIDEO_CAP_ENC_AV1_FEATURE_EXT2: case PIPE_VIDEO_CAP_ENC_AV1_FEATURE_EXT2:
if (sscreen->info.family >= CHIP_GFX1100) { if (sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3) {
union pipe_av1_enc_cap_features_ext2 attrib_ext2; union pipe_av1_enc_cap_features_ext2 attrib_ext2;
attrib_ext2.value = 0; attrib_ext2.value = 0;
@ -760,7 +752,8 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
} else } else
return 0; return 0;
case PIPE_VIDEO_CAP_ENC_SUPPORTS_TILE: case PIPE_VIDEO_CAP_ENC_SUPPORTS_TILE:
if (sscreen->info.family >= CHIP_GFX1100 && profile == PIPE_VIDEO_PROFILE_AV1_MAIN) if ((sscreen->info.vcn_ip_version >= VCN_4_0_0 && sscreen->info.vcn_ip_version != VCN_4_0_3) &&
profile == PIPE_VIDEO_PROFILE_AV1_MAIN)
return 1; return 1;
else else
return 0; return 0;
@ -774,7 +767,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
case PIPE_VIDEO_CAP_SUPPORTED: case PIPE_VIDEO_CAP_SUPPORTED:
if (codec != PIPE_VIDEO_FORMAT_JPEG && if (codec != PIPE_VIDEO_FORMAT_JPEG &&
!(sscreen->info.ip[AMD_IP_UVD].num_queues || !(sscreen->info.ip[AMD_IP_UVD].num_queues ||
((sscreen->info.family >= CHIP_GFX1100 || sscreen->info.family == CHIP_GFX940) ? ((sscreen->info.vcn_ip_version >= VCN_4_0_0) ?
sscreen->info.ip[AMD_IP_VCN_UNIFIED].num_queues : sscreen->info.ip[AMD_IP_VCN_UNIFIED].num_queues :
sscreen->info.ip[AMD_IP_VCN_DEC].num_queues))) sscreen->info.ip[AMD_IP_VCN_DEC].num_queues)))
return false; return false;
@ -785,23 +778,14 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
sscreen->info.family == CHIP_POLARIS11)) sscreen->info.family == CHIP_POLARIS11))
return KERNEL_DEC_CAP(codec, valid); return KERNEL_DEC_CAP(codec, valid);
if (codec < PIPE_VIDEO_FORMAT_MPEG4_AVC && if (codec < PIPE_VIDEO_FORMAT_MPEG4_AVC &&
(sscreen->info.family >= CHIP_NAVI24 || sscreen->info.vcn_ip_version >= VCN_3_0_33)
sscreen->info.family == CHIP_GFX940))
return false; return false;
switch (codec) { switch (codec) {
case PIPE_VIDEO_FORMAT_MPEG12: case PIPE_VIDEO_FORMAT_MPEG12:
if (sscreen->info.gfx_level >= GFX11 || return !(sscreen->info.vcn_ip_version >= VCN_3_0_33 || profile == PIPE_VIDEO_PROFILE_MPEG1);
sscreen->info.family == CHIP_GFX940)
return false;
else
return profile != PIPE_VIDEO_PROFILE_MPEG1;
case PIPE_VIDEO_FORMAT_MPEG4: case PIPE_VIDEO_FORMAT_MPEG4:
if (sscreen->info.gfx_level >= GFX11 || return !(sscreen->info.vcn_ip_version >= VCN_3_0_33);
sscreen->info.family == CHIP_GFX940)
return false;
else
return true;
case PIPE_VIDEO_FORMAT_MPEG4_AVC: case PIPE_VIDEO_FORMAT_MPEG4_AVC:
if ((sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11) && if ((sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11) &&
sscreen->info.uvd_fw_version < UVD_FW_1_66_16) { sscreen->info.uvd_fw_version < UVD_FW_1_66_16) {
@ -810,11 +794,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
} }
return true; return true;
case PIPE_VIDEO_FORMAT_VC1: case PIPE_VIDEO_FORMAT_VC1:
if (sscreen->info.gfx_level >= GFX11 || return !(sscreen->info.vcn_ip_version >= VCN_3_0_33);
sscreen->info.family == CHIP_GFX940)
return false;
else
return true;
case PIPE_VIDEO_FORMAT_HEVC: case PIPE_VIDEO_FORMAT_HEVC:
/* Carrizo only supports HEVC Main */ /* Carrizo only supports HEVC Main */
if (sscreen->info.family >= CHIP_STONEY) if (sscreen->info.family >= CHIP_STONEY)
@ -824,7 +804,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN; return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
return false; return false;
case PIPE_VIDEO_FORMAT_JPEG: case PIPE_VIDEO_FORMAT_JPEG:
if (sscreen->info.family >= CHIP_RAVEN) { if (sscreen->info.vcn_ip_version >= VCN_1_0_0) {
if (!sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues) if (!sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues)
return false; return false;
else else
@ -838,14 +818,9 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
} }
return true; return true;
case PIPE_VIDEO_FORMAT_VP9: case PIPE_VIDEO_FORMAT_VP9:
if (sscreen->info.family < CHIP_RAVEN) return sscreen->info.vcn_ip_version >= VCN_1_0_0;
return false;
return true;
case PIPE_VIDEO_FORMAT_AV1: case PIPE_VIDEO_FORMAT_AV1:
if ((sscreen->info.family < CHIP_NAVI21 && sscreen->info.family != CHIP_GFX940) || return sscreen->info.vcn_ip_version >= VCN_3_0_0 && sscreen->info.vcn_ip_version != VCN_3_0_33;
sscreen->info.family == CHIP_NAVI24)
return false;
return true;
default: default:
return false; return false;
} }
@ -862,7 +837,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
case PIPE_VIDEO_FORMAT_HEVC: case PIPE_VIDEO_FORMAT_HEVC:
case PIPE_VIDEO_FORMAT_VP9: case PIPE_VIDEO_FORMAT_VP9:
case PIPE_VIDEO_FORMAT_AV1: case PIPE_VIDEO_FORMAT_AV1:
return (sscreen->info.family < CHIP_RENOIR) ? return (sscreen->info.vcn_ip_version < VCN_2_0_0) ?
((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) : 8192; ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) : 8192;
default: default:
return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096; return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
@ -876,7 +851,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
case PIPE_VIDEO_FORMAT_HEVC: case PIPE_VIDEO_FORMAT_HEVC:
case PIPE_VIDEO_FORMAT_VP9: case PIPE_VIDEO_FORMAT_VP9:
case PIPE_VIDEO_FORMAT_AV1: case PIPE_VIDEO_FORMAT_AV1:
return (sscreen->info.family < CHIP_RENOIR) ? return (sscreen->info.vcn_ip_version < VCN_2_0_0) ?
((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) : 4352; ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) : 4352;
default: default:
return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096; return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
@ -968,14 +943,14 @@ static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_for
case PIPE_FORMAT_Y8_400_UNORM: case PIPE_FORMAT_Y8_400_UNORM:
return true; return true;
case PIPE_FORMAT_Y8_U8_V8_444_UNORM: case PIPE_FORMAT_Y8_U8_V8_444_UNORM:
if (sscreen->info.family >= CHIP_RENOIR) if (sscreen->info.vcn_ip_version >= VCN_2_0_0)
return true; return true;
else else
return false; return false;
case PIPE_FORMAT_R8G8B8A8_UNORM: case PIPE_FORMAT_R8G8B8A8_UNORM:
case PIPE_FORMAT_A8R8G8B8_UNORM: case PIPE_FORMAT_A8R8G8B8_UNORM:
case PIPE_FORMAT_R8_G8_B8_UNORM: case PIPE_FORMAT_R8_G8_B8_UNORM:
if (sscreen->info.family == CHIP_GFX940) if (sscreen->info.vcn_ip_version == VCN_4_0_3)
return true; return true;
else else
return false; return false;
@ -986,9 +961,10 @@ static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_for
if ((entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) && if ((entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) &&
(((profile == PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH) && (((profile == PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH) &&
(sscreen->info.family >= CHIP_RENOIR)) || (sscreen->info.vcn_ip_version >= VCN_2_0_0)) ||
((profile == PIPE_VIDEO_PROFILE_AV1_MAIN) && ((profile == PIPE_VIDEO_PROFILE_AV1_MAIN) &&
(sscreen->info.family >= CHIP_GFX1100)))) (sscreen->info.vcn_ip_version >= VCN_4_0_0 &&
sscreen->info.vcn_ip_version != VCN_4_0_3))))
return (format == PIPE_FORMAT_P010 || format == PIPE_FORMAT_NV12); return (format == PIPE_FORMAT_P010 || format == PIPE_FORMAT_NV12);
@ -1251,7 +1227,7 @@ void si_init_screen_get_functions(struct si_screen *sscreen)
sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache; sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
if (sscreen->info.ip[AMD_IP_UVD].num_queues || if (sscreen->info.ip[AMD_IP_UVD].num_queues ||
((sscreen->info.family >= CHIP_GFX1100 || sscreen->info.family == CHIP_GFX940) ? ((sscreen->info.vcn_ip_version >= VCN_4_0_0) ?
sscreen->info.ip[AMD_IP_VCN_UNIFIED].num_queues : sscreen->info.ip[AMD_IP_VCN_DEC].num_queues) || sscreen->info.ip[AMD_IP_VCN_UNIFIED].num_queues : sscreen->info.ip[AMD_IP_VCN_DEC].num_queues) ||
sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues || sscreen->info.ip[AMD_IP_VCE].num_queues || sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues || sscreen->info.ip[AMD_IP_VCE].num_queues ||
sscreen->info.ip[AMD_IP_UVD_ENC].num_queues || sscreen->info.ip[AMD_IP_VCN_ENC].num_queues) { sscreen->info.ip[AMD_IP_UVD_ENC].num_queues || sscreen->info.ip[AMD_IP_VCN_ENC].num_queues) {

3
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -519,6 +519,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
sctx->ws = sscreen->ws; sctx->ws = sscreen->ws;
sctx->family = sscreen->info.family; sctx->family = sscreen->info.family;
sctx->gfx_level = sscreen->info.gfx_level; sctx->gfx_level = sscreen->info.gfx_level;
sctx->vcn_ip_ver = sscreen->info.vcn_ip_version;
if (sctx->gfx_level == GFX7 || sctx->gfx_level == GFX8 || sctx->gfx_level == GFX9) { if (sctx->gfx_level == GFX7 || sctx->gfx_level == GFX8 || sctx->gfx_level == GFX9) {
sctx->eop_bug_scratch = si_aligned_buffer_create( sctx->eop_bug_scratch = si_aligned_buffer_create(
@ -710,7 +711,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
/* Initialize multimedia functions. */ /* Initialize multimedia functions. */
if (sscreen->info.ip[AMD_IP_UVD].num_queues || if (sscreen->info.ip[AMD_IP_UVD].num_queues ||
((sscreen->info.family >= CHIP_GFX1100 || sscreen->info.family == CHIP_GFX940) ? ((sscreen->info.vcn_ip_version >= VCN_4_0_0) ?
sscreen->info.ip[AMD_IP_VCN_UNIFIED].num_queues : sscreen->info.ip[AMD_IP_VCN_DEC].num_queues) || sscreen->info.ip[AMD_IP_VCN_UNIFIED].num_queues : sscreen->info.ip[AMD_IP_VCN_DEC].num_queues) ||
sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues || sscreen->info.ip[AMD_IP_VCE].num_queues || sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues || sscreen->info.ip[AMD_IP_VCE].num_queues ||
sscreen->info.ip[AMD_IP_UVD_ENC].num_queues || sscreen->info.ip[AMD_IP_VCN_ENC].num_queues) { sscreen->info.ip[AMD_IP_UVD_ENC].num_queues || sscreen->info.ip[AMD_IP_VCN_ENC].num_queues) {

1
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -1083,6 +1083,7 @@ struct si_context {
/* video context */ /* video context */
bool vcn_has_ctx; bool vcn_has_ctx;
enum vcn_version vcn_ip_ver;
/* shader information */ /* shader information */
uint64_t ps_inputs_read_or_disabled; uint64_t ps_inputs_read_or_disabled;

4
src/gallium/drivers/radeonsi/si_uvd.c
View file

@ -122,7 +122,7 @@ struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templ) const struct pipe_video_codec *templ)
{ {
struct si_context *ctx = (struct si_context *)context; struct si_context *ctx = (struct si_context *)context;
bool vcn = ctx->family >= CHIP_RAVEN; bool vcn = ctx->vcn_ip_ver >= VCN_1_0_0;
if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) { if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
if (vcn) { if (vcn) {
@ -135,7 +135,7 @@ struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
} }
} }
if (ctx->family == CHIP_GFX1100) if (ctx->vcn_ip_ver == VCN_4_0_0)
ctx->vcn_has_ctx = true; ctx->vcn_has_ctx = true;
return (vcn) ? radeon_create_decoder(context, templ) return (vcn) ? radeon_create_decoder(context, templ)