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hk: reindent/unscope
no functional change, split because the diff is all spacing changes. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34585>
This commit is contained in:
Alyssa Rosenzweig
Marge Bot
parent
86d3489c35
commit
ffac153bcf
1 changed files with 101 additions and 105 deletions
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@ -2681,119 +2681,115 @@ hk_flush_dynamic_state(struct hk_cmd_buffer *cmd, struct hk_cs *cs,
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perf_debug(cmd, "Emulating sample mask");
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}
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{
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unsigned samples_shaded = 0;
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if (fs->info.fs.epilog_key.sample_shading)
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samples_shaded = dyn->ms.rasterization_samples;
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unsigned samples_shaded = 0;
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if (fs->info.fs.epilog_key.sample_shading)
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samples_shaded = dyn->ms.rasterization_samples;
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struct hk_fast_link_key_fs key = {
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.prolog.statistics = hk_pipeline_stat_addr(
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cmd,
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VK_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT),
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struct hk_fast_link_key_fs key = {
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.prolog.statistics = hk_pipeline_stat_addr(
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cmd, VK_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT),
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.prolog.cull_distance_size = hw_vs->info.cull_distance_array_size,
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.prolog.api_sample_mask = has_sample_mask ? api_sample_mask : 0xff,
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.nr_samples_shaded = samples_shaded,
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};
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.prolog.cull_distance_size = hw_vs->info.cull_distance_array_size,
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.prolog.api_sample_mask = has_sample_mask ? api_sample_mask : 0xff,
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.nr_samples_shaded = samples_shaded,
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};
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bool prolog_discards =
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has_sample_mask || key.prolog.cull_distance_size;
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bool prolog_discards = has_sample_mask || key.prolog.cull_distance_size;
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bool needs_prolog = key.prolog.statistics || prolog_discards;
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bool needs_prolog = key.prolog.statistics || prolog_discards;
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if (needs_prolog) {
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/* With late main shader tests, the prolog runs tests if neither the
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* main shader nor epilog will.
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*
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* With (nontrivial) early main shader tests, the prolog does not
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* run tests, the tests will run at the start of the main shader.
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* This ensures tests are after API sample mask and cull distance
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* discards.
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*/
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key.prolog.run_zs_tests = !nontrivial_force_early &&
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!fs->b.info.writes_sample_mask &&
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!epilog_discards && prolog_discards;
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if (needs_prolog) {
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/* With late main shader tests, the prolog runs tests if neither the
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* main shader nor epilog will.
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*
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* With (nontrivial) early main shader tests, the prolog does not
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* run tests, the tests will run at the start of the main shader.
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* This ensures tests are after API sample mask and cull distance
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* discards.
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*/
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key.prolog.run_zs_tests = !nontrivial_force_early &&
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!fs->b.info.writes_sample_mask &&
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!epilog_discards && prolog_discards;
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if (key.prolog.cull_distance_size) {
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key.prolog.cf_base = fs->b.info.varyings.fs.nr_cf;
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}
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if (key.prolog.cull_distance_size) {
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key.prolog.cf_base = fs->b.info.varyings.fs.nr_cf;
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}
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key.epilog = (struct agx_fs_epilog_key){
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.link = fs->info.fs.epilog_key,
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.nr_samples = MAX2(dyn->ms.rasterization_samples, 1),
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.blend.alpha_to_coverage = dyn->ms.alpha_to_coverage_enable,
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.blend.alpha_to_one = dyn->ms.alpha_to_one_enable,
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.blend.logicop_enable = dyn->cb.logic_op_enable,
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.blend.logicop_func = vk_logic_op_to_pipe(dyn->cb.logic_op),
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};
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for (unsigned rt = 0; rt < ARRAY_SIZE(dyn->cal.color_map); ++rt) {
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int map = dyn->cal.color_map[rt];
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key.epilog.remap[rt] = map == MESA_VK_ATTACHMENT_UNUSED ? -1 : map;
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}
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if (dyn->ms.alpha_to_one_enable || dyn->ms.alpha_to_coverage_enable ||
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dyn->cb.logic_op_enable) {
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perf_debug(
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cmd, "Epilog with%s%s%s",
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dyn->ms.alpha_to_one_enable ? " alpha-to-one" : "",
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dyn->ms.alpha_to_coverage_enable ? " alpha-to-coverage" : "",
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dyn->cb.logic_op_enable ? " logic-op" : "");
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}
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key.epilog.link.already_ran_zs |= nontrivial_force_early;
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struct hk_rendering_state *render = &cmd->state.gfx.render;
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for (uint32_t i = 0; i < render->color_att_count; i++) {
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key.epilog.rt_formats[i] =
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hk_format_to_pipe_format(render->color_att[i].vk_format);
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const struct vk_color_blend_attachment_state *cb =
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&dyn->cb.attachments[i];
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bool write_enable = dyn->cb.color_write_enables & BITFIELD_BIT(i);
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unsigned write_mask = write_enable ? cb->write_mask : 0;
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/* nir_lower_blend always blends, so use a default blend state when
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* blending is disabled at an API level.
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*/
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if (!dyn->cb.attachments[i].blend_enable) {
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key.epilog.blend.rt[i] = (struct agx_blend_rt_key){
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.colormask = write_mask,
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.rgb_func = PIPE_BLEND_ADD,
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.alpha_func = PIPE_BLEND_ADD,
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.rgb_src_factor = PIPE_BLENDFACTOR_ONE,
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.alpha_src_factor = PIPE_BLENDFACTOR_ONE,
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.rgb_dst_factor = PIPE_BLENDFACTOR_ZERO,
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.alpha_dst_factor = PIPE_BLENDFACTOR_ZERO,
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};
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} else {
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key.epilog.blend.rt[i] = (struct agx_blend_rt_key){
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.colormask = write_mask,
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.rgb_src_factor =
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vk_blend_factor_to_pipe(cb->src_color_blend_factor),
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.rgb_dst_factor =
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vk_blend_factor_to_pipe(cb->dst_color_blend_factor),
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.rgb_func = vk_blend_op_to_pipe(cb->color_blend_op),
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.alpha_src_factor =
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vk_blend_factor_to_pipe(cb->src_alpha_blend_factor),
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.alpha_dst_factor =
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vk_blend_factor_to_pipe(cb->dst_alpha_blend_factor),
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.alpha_func = vk_blend_op_to_pipe(cb->alpha_blend_op),
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};
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}
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}
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hk_update_fast_linked(cmd, fs, &key);
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}
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key.epilog = (struct agx_fs_epilog_key){
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.link = fs->info.fs.epilog_key,
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.nr_samples = MAX2(dyn->ms.rasterization_samples, 1),
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.blend.alpha_to_coverage = dyn->ms.alpha_to_coverage_enable,
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.blend.alpha_to_one = dyn->ms.alpha_to_one_enable,
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.blend.logicop_enable = dyn->cb.logic_op_enable,
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.blend.logicop_func = vk_logic_op_to_pipe(dyn->cb.logic_op),
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};
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for (unsigned rt = 0; rt < ARRAY_SIZE(dyn->cal.color_map); ++rt) {
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int map = dyn->cal.color_map[rt];
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key.epilog.remap[rt] = map == MESA_VK_ATTACHMENT_UNUSED ? -1 : map;
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}
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if (dyn->ms.alpha_to_one_enable || dyn->ms.alpha_to_coverage_enable ||
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dyn->cb.logic_op_enable) {
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perf_debug(
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cmd, "Epilog with%s%s%s",
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dyn->ms.alpha_to_one_enable ? " alpha-to-one" : "",
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dyn->ms.alpha_to_coverage_enable ? " alpha-to-coverage" : "",
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dyn->cb.logic_op_enable ? " logic-op" : "");
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}
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key.epilog.link.already_ran_zs |= nontrivial_force_early;
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struct hk_rendering_state *render = &cmd->state.gfx.render;
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for (uint32_t i = 0; i < render->color_att_count; i++) {
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key.epilog.rt_formats[i] =
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hk_format_to_pipe_format(render->color_att[i].vk_format);
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const struct vk_color_blend_attachment_state *cb =
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&dyn->cb.attachments[i];
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bool write_enable = dyn->cb.color_write_enables & BITFIELD_BIT(i);
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unsigned write_mask = write_enable ? cb->write_mask : 0;
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/* nir_lower_blend always blends, so use a default blend state when
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* blending is disabled at an API level.
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*/
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if (!dyn->cb.attachments[i].blend_enable) {
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key.epilog.blend.rt[i] = (struct agx_blend_rt_key){
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.colormask = write_mask,
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.rgb_func = PIPE_BLEND_ADD,
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.alpha_func = PIPE_BLEND_ADD,
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.rgb_src_factor = PIPE_BLENDFACTOR_ONE,
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.alpha_src_factor = PIPE_BLENDFACTOR_ONE,
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.rgb_dst_factor = PIPE_BLENDFACTOR_ZERO,
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.alpha_dst_factor = PIPE_BLENDFACTOR_ZERO,
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};
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} else {
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key.epilog.blend.rt[i] = (struct agx_blend_rt_key){
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.colormask = write_mask,
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.rgb_src_factor =
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vk_blend_factor_to_pipe(cb->src_color_blend_factor),
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.rgb_dst_factor =
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vk_blend_factor_to_pipe(cb->dst_color_blend_factor),
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.rgb_func = vk_blend_op_to_pipe(cb->color_blend_op),
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.alpha_src_factor =
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vk_blend_factor_to_pipe(cb->src_alpha_blend_factor),
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.alpha_dst_factor =
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vk_blend_factor_to_pipe(cb->dst_alpha_blend_factor),
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.alpha_func = vk_blend_op_to_pipe(cb->alpha_blend_op),
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};
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}
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}
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hk_update_fast_linked(cmd, fs, &key);
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}
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/* If the vertex shader uses draw parameters, vertex uniforms are dirty every
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