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lavapipe: Implement exec graph pipelines
Just a collection of compute shaders that can enqueue each other. Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24512>
This commit is contained in:
Konstantin Seurer
Marge Bot
parent
b817b597c7
commit
ff6a133b72
4 changed files with 389 additions and 3 deletions
181
src/gallium/frontends/lavapipe/lvp_lower_exec_graph.c
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181
src/gallium/frontends/lavapipe/lvp_lower_exec_graph.c
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@ -0,0 +1,181 @@
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/*
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* Copyright © 2023 Valve Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#include "lvp_private.h"
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#include "nir_builder.h"
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#define lvp_load_internal_field(b, bit_size, field) \
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nir_load_ssbo(b, 1, bit_size, nir_imm_int(b, 0), \
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nir_imm_int(b, offsetof(struct lvp_exec_graph_internal_data, field)))
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#define lvp_store_internal_field(b, value, field, scope) \
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nir_store_ssbo(b, value, nir_imm_int(b, 0), \
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nir_iadd_imm(b, \
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nir_imul_imm(b, nir_load_local_invocation_index(b), \
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scope == SCOPE_INVOCATION \
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? sizeof(struct lvp_exec_graph_shader_output) \
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: 0), \
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offsetof(struct lvp_exec_graph_internal_data, outputs) + \
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offsetof(struct lvp_exec_graph_shader_output, field)))
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static bool
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lvp_lower_node_payload_deref(nir_builder *b, nir_instr *instr, void *data)
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{
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if (instr->type != nir_instr_type_deref)
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return false;
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nir_deref_instr *deref = nir_instr_as_deref(instr);
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bool is_payload = nir_deref_mode_is(deref, nir_var_mem_node_payload);
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bool is_payload_in = nir_deref_mode_is(deref, nir_var_mem_node_payload_in);
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if (!is_payload && !is_payload_in)
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return false;
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deref->modes = nir_var_mem_global;
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if (deref->deref_type != nir_deref_type_var)
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return true;
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if (is_payload_in) {
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b->cursor = nir_after_instr(instr);
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nir_def *payload = lvp_load_internal_field(b, 64, payload_in);
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nir_deref_instr *cast = nir_build_deref_cast(b, payload, nir_var_mem_global, deref->type, 0);
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nir_def_rewrite_uses(&deref->def, &cast->def);
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} else {
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nir_foreach_use_safe(use, &deref->def) {
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b->cursor = nir_before_instr(use->parent_instr);
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nir_def *payload = nir_load_var(b, deref->var);
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nir_deref_instr *cast =
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nir_build_deref_cast(b, payload, nir_var_mem_global, deref->type, 0);
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nir_src_rewrite(use, &cast->def);
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}
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}
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nir_instr_remove(instr);
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return true;
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}
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static bool
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lvp_lower_node_payload_derefs(nir_shader *nir)
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{
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return nir_shader_instructions_pass(nir, lvp_lower_node_payload_deref,
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nir_metadata_block_index | nir_metadata_dominance, NULL);
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}
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static void
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lvp_build_initialize_node_payloads(nir_builder *b, nir_intrinsic_instr *intr)
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{
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mesa_scope scope = nir_intrinsic_execution_scope(intr);
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assert(scope == SCOPE_INVOCATION || scope == SCOPE_WORKGROUP);
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nir_deref_instr *payloads_deref = nir_src_as_deref(intr->src[0]);
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assert(payloads_deref->deref_type == nir_deref_type_var);
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nir_variable *payloads_var = payloads_deref->var;
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nir_def *addr = lvp_load_internal_field(b, 64, payloads);
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if (scope == SCOPE_INVOCATION) {
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nir_def *payloads_offset =
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nir_imul_imm(b, nir_load_local_invocation_index(b), b->shader->info.cs.node_payloads_size);
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addr = nir_iadd(b, addr, nir_u2u64(b, payloads_offset));
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}
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nir_store_var(b, payloads_var, addr, 0x1);
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nir_def *payload_count = intr->src[1].ssa;
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lvp_store_internal_field(b, payload_count, payload_count, scope);
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nir_def *node_index = intr->src[1].ssa;
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lvp_store_internal_field(b, node_index, node_index, scope);
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}
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static bool
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lvp_lower_node_payload_intrinsic(nir_builder *b, nir_instr *instr, void *data)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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if (intr->intrinsic == nir_intrinsic_enqueue_node_payloads) {
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nir_instr_remove(instr);
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return false;
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}
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b->cursor = nir_after_instr(instr);
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switch (intr->intrinsic) {
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case nir_intrinsic_initialize_node_payloads:
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lvp_build_initialize_node_payloads(b, intr);
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nir_instr_remove(instr);
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return true;
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case nir_intrinsic_finalize_incoming_node_payload:
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nir_def_rewrite_uses(&intr->def, nir_imm_true(b));
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nir_instr_remove(instr);
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return true;
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case nir_intrinsic_load_coalesced_input_count:
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nir_def_rewrite_uses(&intr->def, nir_imm_int(b, 1));
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nir_instr_remove(instr);
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return true;
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default:
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return false;
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}
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}
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static bool
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lvp_lower_exec_graph_intrinsics(nir_shader *nir)
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{
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return nir_shader_instructions_pass(nir, lvp_lower_node_payload_intrinsic,
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nir_metadata_block_index | nir_metadata_dominance, NULL);
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}
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static void
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lvp_lower_node_payload_vars(struct lvp_pipeline *pipeline, nir_shader *nir)
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{
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nir_foreach_variable_in_shader(var, nir) {
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if (var->data.mode != nir_var_mem_node_payload &&
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var->data.mode != nir_var_mem_node_payload_in)
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continue;
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if (var->data.mode == nir_var_mem_node_payload) {
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assert(var->data.node_name);
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assert(!pipeline->exec_graph.next_name);
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pipeline->exec_graph.next_name = var->data.node_name;
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}
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var->data.mode = nir_var_shader_temp;
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var->type = glsl_uint64_t_type();
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}
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}
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bool
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lvp_lower_exec_graph(struct lvp_pipeline *pipeline, nir_shader *nir)
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{
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bool progress = false;
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NIR_PASS(progress, nir, nir_lower_vars_to_explicit_types,
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nir_var_mem_node_payload | nir_var_mem_node_payload_in,
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glsl_get_natural_size_align_bytes);
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if (!progress)
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return false;
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/* Lower node payload variables to 64-bit addresses. */
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lvp_lower_node_payload_vars(pipeline, nir);
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/* Lower exec graph intrinsics to their actual implementation. */
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lvp_lower_exec_graph_intrinsics(nir);
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/* Lower node payloads to load/store_global intructions. */
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lvp_lower_node_payload_derefs(nir);
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NIR_PASS(_, nir, nir_lower_explicit_io, nir_var_mem_global, nir_address_format_64bit_global);
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/* Cleanup passes */
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NIR_PASS(_, nir, nir_lower_global_vars_to_local);
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NIR_PASS(_, nir, nir_lower_vars_to_ssa);
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NIR_PASS(_, nir, nir_opt_constant_folding);
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NIR_PASS(_, nir, nir_opt_dce);
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return true;
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}
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@ -279,6 +279,11 @@ compile_spirv(struct lvp_device *pdevice, const VkPipelineShaderStageCreateInfo
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assert(stage <= LVP_SHADER_STAGES && stage != MESA_SHADER_NONE);
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VkResult result;
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#ifdef VK_ENABLE_BETA_EXTENSIONS
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const VkPipelineShaderStageNodeCreateInfoAMDX *node_info = vk_find_struct_const(
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sinfo->pNext, PIPELINE_SHADER_STAGE_NODE_CREATE_INFO_AMDX);
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#endif
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const struct spirv_to_nir_options spirv_options = {
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.environment = NIR_SPIRV_VULKAN,
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.caps = {
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@ -333,6 +338,9 @@ compile_spirv(struct lvp_device *pdevice, const VkPipelineShaderStageCreateInfo
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.phys_ssbo_addr_format = nir_address_format_64bit_global,
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.push_const_addr_format = nir_address_format_logical,
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.shared_addr_format = nir_address_format_32bit_offset,
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#ifdef VK_ENABLE_BETA_EXTENSIONS
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.shader_index = node_info ? node_info->index : 0,
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#endif
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};
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result = vk_pipeline_shader_stage_to_nir(&pdevice->vk, sinfo,
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@ -367,8 +375,9 @@ lvp_ycbcr_conversion_lookup(const void *data, uint32_t set, uint32_t binding, ui
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return ycbcr_conversion ? &ycbcr_conversion->state : NULL;
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}
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/* pipeline is NULL for shader objects. */
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static void
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lvp_shader_lower(struct lvp_device *pdevice, nir_shader *nir, struct lvp_shader *shader, struct lvp_pipeline_layout *layout)
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lvp_shader_lower(struct lvp_device *pdevice, struct lvp_pipeline *pipeline, nir_shader *nir, struct lvp_shader *shader, struct lvp_pipeline_layout *layout)
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{
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if (nir->info.stage != MESA_SHADER_TESS_CTRL)
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NIR_PASS_V(nir, remove_barriers, nir->info.stage == MESA_SHADER_COMPUTE || nir->info.stage == MESA_SHADER_MESH || nir->info.stage == MESA_SHADER_TASK);
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@ -413,6 +422,9 @@ lvp_shader_lower(struct lvp_device *pdevice, nir_shader *nir, struct lvp_shader
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nir_var_mem_global,
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nir_address_format_64bit_global);
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if (nir->info.stage == MESA_SHADER_COMPUTE)
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lvp_lower_exec_graph(pipeline, nir);
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NIR_PASS(_, nir, nir_vk_lower_ycbcr_tex, lvp_ycbcr_conversion_lookup, layout);
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nir_lower_non_uniform_access_options options = {
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@ -492,7 +504,7 @@ lvp_shader_compile_to_ir(struct lvp_pipeline *pipeline,
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nir_shader *nir;
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VkResult result = compile_spirv(pdevice, sinfo, &nir);
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if (result == VK_SUCCESS)
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lvp_shader_lower(pdevice, nir, shader, pipeline->layout);
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lvp_shader_lower(pdevice, pipeline, nir, shader, pipeline->layout);
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return result;
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}
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@ -1027,6 +1039,12 @@ get_pipeline_create_flags(const void *pCreateInfo)
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const VkRayTracingPipelineCreateInfoKHR *create_info = (VkRayTracingPipelineCreateInfoKHR *)pCreateInfo;
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return create_info->flags;
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}
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#ifdef VK_ENABLE_BETA_EXTENSIONS
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case VK_STRUCTURE_TYPE_EXECUTION_GRAPH_PIPELINE_CREATE_INFO_AMDX: {
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const VkExecutionGraphPipelineCreateInfoAMDX *create_info = (VkExecutionGraphPipelineCreateInfoAMDX *)pCreateInfo;
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return create_info->flags;
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}
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#endif
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default:
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unreachable("invalid pCreateInfo pipeline struct");
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}
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@ -1263,7 +1281,7 @@ create_shader_object(struct lvp_device *device, const VkShaderCreateInfoEXT *pCr
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pCreateInfo->pPushConstantRanges,
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};
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shader->layout = lvp_pipeline_layout_create(device, &pci, pAllocator);
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lvp_shader_lower(device, nir, shader, shader->layout);
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lvp_shader_lower(device, NULL, nir, shader, shader->layout);
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lvp_shader_xfb_init(shader);
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if (stage == MESA_SHADER_TESS_EVAL) {
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/* spec requires that all tess modes are set in both shaders */
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@ -1339,3 +1357,163 @@ VKAPI_ATTR VkResult VKAPI_CALL lvp_GetShaderBinaryDataEXT(
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}
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return ret;
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}
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#ifdef VK_ENABLE_BETA_EXTENSIONS
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static VkResult
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lvp_exec_graph_pipeline_create(VkDevice _device, VkPipelineCache _cache,
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const VkExecutionGraphPipelineCreateInfoAMDX *create_info,
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VkPipelineCreateFlagBits2KHR flags,
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VkPipeline *out_pipeline)
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{
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LVP_FROM_HANDLE(lvp_device, device, _device);
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struct lvp_pipeline *pipeline;
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VkResult result;
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assert(create_info->sType == VK_STRUCTURE_TYPE_EXECUTION_GRAPH_PIPELINE_CREATE_INFO_AMDX);
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uint32_t stage_count = create_info->stageCount;
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if (create_info->pLibraryInfo) {
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for (uint32_t i = 0; i < create_info->pLibraryInfo->libraryCount; i++) {
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VK_FROM_HANDLE(lvp_pipeline, library, create_info->pLibraryInfo->pLibraries[i]);
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stage_count += library->num_groups;
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}
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}
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pipeline = vk_zalloc(&device->vk.alloc, sizeof(*pipeline) + stage_count * sizeof(VkPipeline), 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (!pipeline)
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return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
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vk_object_base_init(&device->vk, &pipeline->base,
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VK_OBJECT_TYPE_PIPELINE);
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uint64_t t0 = os_time_get_nano();
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pipeline->type = LVP_PIPELINE_EXEC_GRAPH;
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pipeline->layout = lvp_pipeline_layout_from_handle(create_info->layout);
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pipeline->exec_graph.scratch_size = 0;
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pipeline->num_groups = stage_count;
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uint32_t stage_index = 0;
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for (uint32_t i = 0; i < create_info->stageCount; i++) {
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const VkPipelineShaderStageNodeCreateInfoAMDX *node_info = vk_find_struct_const(
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create_info->pStages[i].pNext, PIPELINE_SHADER_STAGE_NODE_CREATE_INFO_AMDX);
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VkComputePipelineCreateInfo stage_create_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.flags = create_info->flags,
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.stage = create_info->pStages[i],
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.layout = create_info->layout,
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};
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result = lvp_compute_pipeline_create(_device, _cache, &stage_create_info, flags, &pipeline->groups[i]);
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if (result != VK_SUCCESS)
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goto fail;
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VK_FROM_HANDLE(lvp_pipeline, stage, pipeline->groups[i]);
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nir_shader *nir = stage->shaders[MESA_SHADER_COMPUTE].pipeline_nir->nir;
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if (node_info) {
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stage->exec_graph.name = node_info->pName;
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stage->exec_graph.index = node_info->index;
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}
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/* TODO: Add a shader info NIR pass to figure out how many the payloads the shader creates. */
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stage->exec_graph.scratch_size = nir->info.cs.node_payloads_size * 256;
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pipeline->exec_graph.scratch_size = MAX2(pipeline->exec_graph.scratch_size, stage->exec_graph.scratch_size);
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stage_index++;
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}
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if (create_info->pLibraryInfo) {
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for (uint32_t i = 0; i < create_info->pLibraryInfo->libraryCount; i++) {
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VK_FROM_HANDLE(lvp_pipeline, library, create_info->pLibraryInfo->pLibraries[i]);
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for (uint32_t j = 0; j < library->num_groups; j++) {
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/* TODO: Do we need reference counting? */
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pipeline->groups[stage_index] = library->groups[j];
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stage_index++;
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}
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pipeline->exec_graph.scratch_size = MAX2(pipeline->exec_graph.scratch_size, library->exec_graph.scratch_size);
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}
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}
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const VkPipelineCreationFeedbackCreateInfo *feedback = (void*)vk_find_struct_const(create_info->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO);
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if (feedback) {
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feedback->pPipelineCreationFeedback->duration = os_time_get_nano() - t0;
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feedback->pPipelineCreationFeedback->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT;
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memset(feedback->pPipelineStageCreationFeedbacks, 0, sizeof(VkPipelineCreationFeedback) * feedback->pipelineStageCreationFeedbackCount);
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}
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*out_pipeline = lvp_pipeline_to_handle(pipeline);
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return VK_SUCCESS;
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fail:
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for (uint32_t i = 0; i < stage_count; i++)
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lvp_DestroyPipeline(_device, pipeline->groups[i], NULL);
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vk_free(&device->vk.alloc, pipeline);
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return result;
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}
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VKAPI_ATTR VkResult VKAPI_CALL
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lvp_CreateExecutionGraphPipelinesAMDX(VkDevice device, VkPipelineCache pipelineCache,
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uint32_t createInfoCount,
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const VkExecutionGraphPipelineCreateInfoAMDX *pCreateInfos,
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const VkAllocationCallbacks *pAllocator,
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VkPipeline *pPipelines)
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{
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VkResult result = VK_SUCCESS;
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uint32_t i = 0;
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for (; i < createInfoCount; i++) {
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VkPipelineCreateFlagBits2KHR flags = get_pipeline_create_flags(&pCreateInfos[i]);
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VkResult r = VK_PIPELINE_COMPILE_REQUIRED;
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if (!(flags & VK_PIPELINE_CREATE_2_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_KHR))
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r = lvp_exec_graph_pipeline_create(device, pipelineCache, &pCreateInfos[i], flags, &pPipelines[i]);
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||||
if (r != VK_SUCCESS) {
|
||||
result = r;
|
||||
pPipelines[i] = VK_NULL_HANDLE;
|
||||
if (flags & VK_PIPELINE_CREATE_2_EARLY_RETURN_ON_FAILURE_BIT_KHR)
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (result != VK_SUCCESS) {
|
||||
for (; i < createInfoCount; i++)
|
||||
pPipelines[i] = VK_NULL_HANDLE;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
VKAPI_ATTR VkResult VKAPI_CALL
|
||||
lvp_GetExecutionGraphPipelineScratchSizeAMDX(VkDevice device, VkPipeline executionGraph,
|
||||
VkExecutionGraphPipelineScratchSizeAMDX *pSizeInfo)
|
||||
{
|
||||
VK_FROM_HANDLE(lvp_pipeline, pipeline, executionGraph);
|
||||
pSizeInfo->size = MAX2(pipeline->exec_graph.scratch_size * 32, 16);
|
||||
return VK_SUCCESS;
|
||||
}
|
||||
|
||||
VKAPI_ATTR VkResult VKAPI_CALL
|
||||
lvp_GetExecutionGraphPipelineNodeIndexAMDX(VkDevice device, VkPipeline executionGraph,
|
||||
const VkPipelineShaderStageNodeCreateInfoAMDX *pNodeInfo,
|
||||
uint32_t *pNodeIndex)
|
||||
{
|
||||
VK_FROM_HANDLE(lvp_pipeline, pipeline, executionGraph);
|
||||
|
||||
for (uint32_t i = 0; i < pipeline->num_groups; i++) {
|
||||
VK_FROM_HANDLE(lvp_pipeline, stage, pipeline->groups[i]);
|
||||
if (stage->exec_graph.index == pNodeInfo->index &&
|
||||
!strcmp(stage->exec_graph.name, pNodeInfo->pName)) {
|
||||
*pNodeIndex = i;
|
||||
return VK_SUCCESS;
|
||||
}
|
||||
}
|
||||
|
||||
return VK_ERROR_OUT_OF_HOST_MEMORY;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -495,11 +495,37 @@ struct lvp_pipeline {
|
|||
bool compiled;
|
||||
bool used;
|
||||
|
||||
struct {
|
||||
const char *name;
|
||||
const char *next_name;
|
||||
uint32_t index;
|
||||
uint32_t scratch_size;
|
||||
} exec_graph;
|
||||
|
||||
unsigned num_groups;
|
||||
unsigned num_groups_total;
|
||||
VkPipeline groups[0];
|
||||
};
|
||||
|
||||
/* Minimum requirement by the spec. */
|
||||
#define LVP_MAX_EXEC_GRAPH_PAYLOADS 256
|
||||
|
||||
struct lvp_exec_graph_shader_output {
|
||||
uint32_t payload_count;
|
||||
uint32_t node_index;
|
||||
};
|
||||
|
||||
struct lvp_exec_graph_internal_data {
|
||||
/* inputs */
|
||||
void *payload_in;
|
||||
void *payloads;
|
||||
/* outputs */
|
||||
struct lvp_exec_graph_shader_output outputs[LVP_MAX_EXEC_GRAPH_PAYLOADS];
|
||||
};
|
||||
|
||||
bool
|
||||
lvp_lower_exec_graph(struct lvp_pipeline *pipeline, nir_shader *nir);
|
||||
|
||||
void
|
||||
lvp_pipeline_shaders_compile(struct lvp_pipeline *pipeline, bool locked);
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ liblvp_files = files(
|
|||
'lvp_image.c',
|
||||
'lvp_formats.c',
|
||||
'lvp_inline_uniforms.c',
|
||||
'lvp_lower_exec_graph.c',
|
||||
'lvp_lower_vulkan_resource.c',
|
||||
'lvp_lower_vulkan_resource.h',
|
||||
'lvp_lower_input_attachments.c',
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue