From ff529f95826a5aa6b5d6c7e5d6e088fb6905fe55 Mon Sep 17 00:00:00 2001 From: Sviatoslav Peleshko Date: Sun, 6 Jul 2025 23:58:29 +0300 Subject: [PATCH] brw/disasm: Fix Gfx11 3src-instructions dst register disassembly The conversion from bit value to register file type is already done by the brw_eu_inst_3src_a1_dst_reg_file in the FFC macro now, so doing it again produced incorrect results. Fixes: e7179232 ("intel/brw: Move encoding of Gfx11 3-src inside the inst helpers") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13141 Signed-off-by: Sviatoslav Peleshko Reviewed-by: Caio Oliveira Part-of: (cherry picked from commit 8d22eb960b7246dd65aefbe581c443fdc2746541) --- .pick_status.json | 2 +- src/intel/compiler/brw_disasm.c | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 6056c9bc145..2b151d832a7 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -5794,7 +5794,7 @@ "description": "brw/disasm: Fix Gfx11 3src-instructions dst register disassembly", "nominated": true, "nomination_type": 2, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "e7179232c9d8968f45687c795323ef2b39719a2d", "notes": null diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index dd23be6b701..2374d64de31 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -977,10 +977,8 @@ dest_3src(FILE *file, const struct intel_device_info *devinfo, if (devinfo->ver < 10 && is_align1) return 0; - if (devinfo->ver >= 12) + if (devinfo->ver >= 12 || is_align1) reg_file = brw_eu_inst_3src_a1_dst_reg_file(devinfo, inst); - else if (is_align1 && brw_eu_inst_3src_a1_dst_reg_file(devinfo, inst)) - reg_file = ARF; else reg_file = FIXED_GRF;