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amd/registers: fix parse_kernel_headers.py warnings by adding missing enums

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Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19419>
This commit is contained in:
Marek Olšák 2022-10-21 14:01:31 -04:00 • committed by Marge Bot
parent c4104482c8
commit ff4cd2133d
2 changed files with 43 additions and 7 deletions
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22
src/amd/registers/gfx9.json
View file

@ -68,6 +68,15 @@
{"name": "ADDR_SURF_BANK_WIDTH_8", "value": 3}
]
},
"BinSizeExtend": {
"entries": [
{"name": "BIN_SIZE_32_PIXELS", "value": 0},
{"name": "BIN_SIZE_64_PIXELS", "value": 1},
{"name": "BIN_SIZE_128_PIXELS", "value": 2},
{"name": "BIN_SIZE_256_PIXELS", "value": 3},
{"name": "BIN_SIZE_512_PIXELS", "value": 4}
]
},
"BinningMode": {
"entries": [
{"name": "BINNING_ALLOWED", "value": 0},
@ -822,6 +831,13 @@
{"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}
]
},
"ScUncertaintyRegionMode": {
"entries": [
{"name": "SC_HALF_LSB", "value": 0},
{"name": "SC_LSB_ONE_SIDED", "value": 1},
{"name": "SC_LSB_TWO_SIDED", "value": 2}
]
},
"ScXsel": {
"entries": [
{"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},
@ -11972,8 +11988,8 @@
{"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"},
{"bits": [2, 2], "name": "BIN_SIZE_X"},
{"bits": [3, 3], "name": "BIN_SIZE_Y"},
{"bits": [4, 6], "name": "BIN_SIZE_X_EXTEND"},
{"bits": [7, 9], "name": "BIN_SIZE_Y_EXTEND"},
{"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"},
{"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"},
{"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"},
{"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"},
{"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"},
@ -12035,7 +12051,7 @@
{"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"},
{"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"},
{"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"},
{"bits": [16, 17], "name": "UNCERTAINTY_REGION_MODE"},
{"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE"},
{"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"},
{"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"},
{"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"},

28
src/amd/registers/parse_kernel_headers.py
View file

@ -564,6 +564,29 @@ missing_enums_gfx81plus = {
},
}
missing_enums_gfx9 = {
**missing_enums_gfx81plus,
"DB_DFSM_CONTROL__PUNCHOUT_MODE": DB_DFSM_CONTROL__PUNCHOUT_MODE,
"IMG_DATA_FORMAT_STENCIL": IMG_DATA_FORMAT_STENCIL,
"SQ_IMG_RSRC_WORD4__BC_SWIZZLE": SQ_IMG_RSRC_WORD4__BC_SWIZZLE,
"BinSizeExtend": {
"entries": [
{"name": "BIN_SIZE_32_PIXELS", "value": 0},
{"name": "BIN_SIZE_64_PIXELS", "value": 1},
{"name": "BIN_SIZE_128_PIXELS", "value": 2},
{"name": "BIN_SIZE_256_PIXELS", "value": 3},
{"name": "BIN_SIZE_512_PIXELS", "value": 4}
]
},
"ScUncertaintyRegionMode": {
"entries": [
{"name": "SC_HALF_LSB", "value": 0},
{"name": "SC_LSB_ONE_SIDED", "value": 1},
{"name": "SC_LSB_TWO_SIDED", "value": 2}
]
},
}
missing_enums_gfx103plus = {
**missing_enums_gfx81plus,
"ColorFormat": ColorFormat,
@ -624,10 +647,7 @@ enums_missing = {
**missing_enums_gfx81plus,
},
'gfx9': {
**missing_enums_gfx81plus,
"DB_DFSM_CONTROL__PUNCHOUT_MODE": DB_DFSM_CONTROL__PUNCHOUT_MODE,
"IMG_DATA_FORMAT_STENCIL": IMG_DATA_FORMAT_STENCIL,
"SQ_IMG_RSRC_WORD4__BC_SWIZZLE": SQ_IMG_RSRC_WORD4__BC_SWIZZLE,
**missing_enums_gfx9,
},
'gfx10': {
**missing_enums_gfx81plus,