intel/brw: Update outdated comments

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32536>

src/intel/compiler/brw_eu_validate.c

@@ -1888,7 +1888,7 @@ instruction_restrictions(const struct brw_isa_info *isa,
        *
        * The same text also appears for OR, NOT, and XOR instructions.
        *
-       * Per the comment around nir_op_imod in brw_fs_nir.cpp, we have
+       * Per the comment around nir_op_imod in brw_from_nir.cpp, we have
        * determined this to not be true. The only conditions that seem
        * absolutely sketchy are O, R, and U.  Some OpenGL shaders from Doom
        * 2016 have been observed to generate and.g and operate correctly.

src/intel/compiler/brw_lower_logical_sends.cpp

@@ -2149,7 +2149,7 @@ lower_interpolator_logical_send(const brw_builder &bld, brw_inst *inst,
       const brw_builder &ubld = bld.exec_all().group(8, 0);
       desc = ubld.vgrf(BRW_TYPE_UD);
 
-      /* The predicate should have been built in brw_fs_nir.cpp when emitting
+      /* The predicate should have been built in brw_from_nir.cpp when emitting
        * NIR code. This guarantees that we do not have incorrect interactions
        * with the flag register holding the predication result.
        */
@@ -2272,7 +2272,7 @@ static void
 lower_trace_ray_logical_send(const brw_builder &bld, brw_inst *inst)
 {
    const intel_device_info *devinfo = bld.shader->devinfo;
-   /* The emit_uniformize() in brw_fs_nir.cpp will generate an horizontal
+   /* The emit_uniformize() in brw_from_nir.cpp will generate an horizontal
     * stride of 0. Below we're doing a MOV() in SIMD2. Since we can't use UQ/Q
     * types in on Gfx12.5, we need to tweak the stride with a value of 1 dword
     * so that the MOV operates on 2 components rather than twice the same
@@ -2370,7 +2370,7 @@ lower_get_buffer_size(const brw_builder &bld, brw_inst *inst)
 {
    const intel_device_info *devinfo = bld.shader->devinfo;
    /* Since we can only execute this instruction on uniform bti/surface
-    * handles, brw_fs_nir.cpp should already have limited this to SIMD8.
+    * handles, brw_from_nir.cpp should already have limited this to SIMD8.
     */
    assert(inst->exec_size == (devinfo->ver < 20 ? 8 : 16));
 

src/intel/compiler/brw_opt.cpp

@@ -185,7 +185,7 @@ brw_optimize(brw_shader &s)
 
    if (OPT(brw_lower_send_descriptors)) {
       /* No need for standard copy_propagation since
-       * brw_fs_opt_address_reg_load will only optimize defs.
+       * brw_opt_address_reg_load will only optimize defs.
        */
       if (OPT(brw_opt_copy_propagation_defs))
          OPT(brw_opt_algebraic);

src/intel/compiler/brw_opt_address_reg_load.cpp

@@ -8,7 +8,7 @@
 #include "brw_cfg.h"
 #include "brw_eu.h"
 
-/** @file brw_fs_opt_address_reg_load.cpp
+/** @file
  *
  * Turn this sequence :
  *

src/intel/compiler/brw_opt_copy_propagation.cpp

@@ -1098,7 +1098,7 @@ try_constant_propagate_value(const intel_device_info *devinfo,
           *    When multiplying a DW and any lower precision integer, the
           *    DW operand must on src0.
           *
-          * So it would have been invalid. However, brw_fs_combine_constants
+          * So it would have been invalid. However, brw_opt_combine_constants
           * will now "fix" the constant.
           */
          if (inst->opcode == BRW_OPCODE_MUL &&

src/intel/compiler/brw_reg_allocate.cpp

@@ -362,10 +362,6 @@ namespace {
        *            allocated to hold the result of the instruction (and the
        *            scratch write header).
        */
-      /* FINISHME - The shader's dispatch width probably belongs in
-       *            backend_shader (or some nonexistent fs_shader class?)
-       *            rather than in the visitor class.
-       */
       return s->dispatch_width / 8;
    }
 }

src/intel/compiler/brw_schedule_instructions.cpp

@@ -1256,7 +1256,7 @@ brw_instruction_scheduler::calculate_deps()
       /* Address registers have virtual identifier, allowing us to identify
        * what instructions needs the values written to the register. The
        * address register is written/read in pairs of instructions (enforced
-       * by the brw_fs_validate.cpp).
+       * by the brw_validate.cpp).
        *
        * To allow scheduling of SEND messages, out of order, without the
        * address register tracking generating serialized dependency between

src/intel/compiler/brw_shader.cpp

@@ -847,7 +847,7 @@ brw_shader::convert_attr_sources_to_hw_regs(brw_inst *inst)
                    prog_data->curb_read_length +
                    inst->src[i].offset / REG_SIZE;
 
-         /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
+         /* As explained at brw_lower_vgrf_to_fixed_grf, From the Haswell PRM:
           *
           * VertStride must be used to cross GRF register boundaries. This
           * rule implies that elements within a 'Width' cannot cross GRF