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i965: Reconnect the index/vertex setup.

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This commit is contained in:
Eric Anholt 2009-12-03 16:53:07 -08:00
parent c9dc6d425e
commit ff3997904a
4 changed files with 40 additions and 15 deletions
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5
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -784,14 +784,19 @@
#define CMD_VERTEX_BUFFER 0x7808
# define BRW_VB0_INDEX_SHIFT 27
# define GEN6_VB0_INDEX_SHIFT 26
# define BRW_VB0_ACCESS_VERTEXDATA (0 << 26)
# define BRW_VB0_ACCESS_INSTANCEDATA (1 << 26)
# define GEN6_VB0_ACCESS_VERTEXDATA (0 << 20)
# define GEN6_VB0_ACCESS_INSTANCEDATA (1 << 20)
# define BRW_VB0_PITCH_SHIFT 0
#define CMD_VERTEX_ELEMENT 0x7809
# define BRW_VE0_INDEX_SHIFT 27
# define GEN6_VE0_INDEX_SHIFT 26
# define BRW_VE0_FORMAT_SHIFT 16
# define BRW_VE0_VALID (1 << 26)
# define GEN6_VE0_VALID (1 << 25)
# define BRW_VE0_SRC_OFFSET_SHIFT 0
# define BRW_VE1_COMPONENT_NOSTORE 0
# define BRW_VE1_COMPONENT_STORE_SRC 1

42
src/mesa/drivers/dri/i965/brw_draw_upload.c
View file

@ -503,10 +503,17 @@ static void brw_emit_vertices(struct brw_context *brw)
if (brw->vb.nr_enabled == 0) {
BEGIN_BATCH(3);
OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | 1);
OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
BRW_VE0_VALID |
(BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
(0 << BRW_VE0_SRC_OFFSET_SHIFT));
if (IS_GEN6(intel->intelScreen->deviceID)) {
OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
GEN6_VE0_VALID |
(BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
(0 << BRW_VE0_SRC_OFFSET_SHIFT));
} else {
OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
BRW_VE0_VALID |
(BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
(0 << BRW_VE0_SRC_OFFSET_SHIFT));
}
OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
(BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
(BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
@ -527,9 +534,17 @@ static void brw_emit_vertices(struct brw_context *brw)
for (i = 0; i < brw->vb.nr_enabled; i++) {
struct brw_vertex_element *input = brw->vb.enabled[i];
uint32_t dw0;
OUT_BATCH((i << BRW_VB0_INDEX_SHIFT) |
BRW_VB0_ACCESS_VERTEXDATA |
if (IS_GEN6(intel->intelScreen->deviceID)) {
dw0 = GEN6_VB0_ACCESS_VERTEXDATA |
(i << GEN6_VB0_INDEX_SHIFT);
} else {
dw0 = BRW_VB0_ACCESS_VERTEXDATA |
(i << BRW_VB0_INDEX_SHIFT);
}
OUT_BATCH(dw0 |
(input->stride << BRW_VB0_PITCH_SHIFT));
OUT_RELOC(input->bo,
I915_GEM_DOMAIN_VERTEX, 0,
@ -565,10 +580,17 @@ static void brw_emit_vertices(struct brw_context *brw)
break;
}
OUT_BATCH((i << BRW_VE0_INDEX_SHIFT) |
BRW_VE0_VALID |
(format << BRW_VE0_FORMAT_SHIFT) |
(0 << BRW_VE0_SRC_OFFSET_SHIFT));
if (IS_GEN6(intel->intelScreen->deviceID)) {
OUT_BATCH((i << GEN6_VE0_INDEX_SHIFT) |
GEN6_VE0_VALID |
(format << BRW_VE0_FORMAT_SHIFT) |
(0 << BRW_VE0_SRC_OFFSET_SHIFT));
} else {
OUT_BATCH((i << BRW_VE0_INDEX_SHIFT) |
BRW_VE0_VALID |
(format << BRW_VE0_FORMAT_SHIFT) |
(0 << BRW_VE0_SRC_OFFSET_SHIFT));
}
if (intel->is_ironlake)
OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |

5
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -163,12 +163,11 @@ const struct brw_tracked_state *gen6_atoms[] =
&brw_psp_urb_cbs,
&brw_drawing_rect,
#endif
&brw_indices,
&brw_index_buffer,
&brw_vertices,
&brw_constant_buffer
#endif
};
void brw_init_state( struct brw_context *brw )

3
src/mesa/drivers/dri/i965/gen6_vs_state.c
View file

@ -54,8 +54,7 @@ upload_vs_state(struct brw_context *brw)
OUT_BATCH(0); /* scratch space base offset */
OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
(brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT) |
GEN6_VS_ENABLE);
(0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
GEN6_VS_STATISTICS_ENABLE);
ADVANCE_BATCH();