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freedreno/a7xx: Register updates from kgsl

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Will be necessary for kernel changes to match kgsl.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28883>
This commit is contained in:
Connor Abbott 2024-04-23 19:35:18 +02:00 • committed by Marge Bot
parent 59d3a8ea07
commit ff155f46a3
6 changed files with 18 additions and 9 deletions
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2
src/freedreno/.gitlab-ci/reference/crash.log
View file

@ -1550,7 +1550,7 @@ registers:
00000000 0x8e23: 00000000
00000000 0x8e24: 00000000
00000000 0x8e25: 00000000
00000000 RB_UNKNOWN_8E28: 0
00000000 RB_CMP_DBG_ECO_CNTL: 0
00000000 RB_PERFCTR_CMP_SEL[0]+0: 00000000
00000000 RB_PERFCTR_CMP_SEL[0x1]+0: 00000000
00000000 RB_PERFCTR_CMP_SEL[0x2]+0: 00000000

2
src/freedreno/.gitlab-ci/reference/crash_prefetch.log
View file

@ -1765,7 +1765,7 @@ registers:
00000000 0x8e23: 00000000
00000000 0x8e24: 00000000
00000000 0x8e25: 00000000
00000000 RB_UNKNOWN_8E28: 0
00000000 RB_CMP_DBG_ECO_CNTL: 0
00000000 RB_PERFCTR_CMP_SEL[0]+0: 00000000
00000000 RB_PERFCTR_CMP_SEL[0x1]+0: 00000000
00000000 RB_PERFCTR_CMP_SEL[0x2]+0: 00000000

2
src/freedreno/.gitlab-ci/reference/prefetch-test.log
View file

@ -2344,7 +2344,7 @@ registers:
00000000 0x8e23: 00000000
00000000 0x8e24: 00000000
00000000 0x8e25: 00000000
00000000 RB_UNKNOWN_8E28: 0
00000000 RB_CMP_DBG_ECO_CNTL: 0
00000000 RB_PERFCTR_CMP_SEL[0]+0: 00000000
00000000 RB_PERFCTR_CMP_SEL[0x1]+0: 00000000
00000000 RB_PERFCTR_CMP_SEL[0x2]+0: 00000000

4
src/freedreno/common/freedreno_devices.py
View file

@ -841,7 +841,7 @@ a730_magic_regs = dict(
a730_raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00840004],
[A6XXRegs.REG_A6XX_TPL1_UNKNOWN_B602, 0x00000724],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000724],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00002400],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00000000],
@ -957,7 +957,7 @@ add_gpus([
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00040004],
[A6XXRegs.REG_A6XX_TPL1_UNKNOWN_B602, 0x00000724],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000724],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00000400],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00430800],

4
src/freedreno/common/freedreno_stompable_regs.h
View file

@ -46,7 +46,7 @@ fd_reg_stomp_allowed(chip CHIP, uint16_t reg)
case REG_A6XX_SP_FS_OBJ_START ... REG_A6XX_SP_FS_OBJ_START + 1:
return false;
/* Not used on A6XX but causes failures when set */
case REG_A6XX_TPL1_UNKNOWN_B602:
case REG_A6XX_TPL1_DBG_ECO_CNTL1:
return false;
}
break;
@ -67,7 +67,7 @@ fd_reg_stomp_allowed(chip CHIP, uint16_t reg)
case REG_A7XX_SP_UNKNOWN_AE73:
case REG_A7XX_RB_UNKNOWN_8E79:
case REG_A7XX_SP_UNKNOWN_AE09:
case REG_A6XX_TPL1_UNKNOWN_B602:
case REG_A6XX_TPL1_DBG_ECO_CNTL:
return false;
case REG_A7XX_SP_GS_VGPR_CONFIG:
case REG_A7XX_SP_FS_VGPR_CONFIG:

13
src/freedreno/registers/adreno/a6xx.xml
View file

@ -1227,6 +1227,7 @@ to upconvert to 32b float internally?
<bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
<bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
<bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX-"/>
<bitfield name="SWFUSEVIOLATION" pos="29" type="boolean" variants="A7XX-"/>
<bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
<bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
</bitset>
@ -1503,6 +1504,9 @@ to upconvert to 32b float internally?
<reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/>
<reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/>
<reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX-"/>
<reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX-"/>
<array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/>
<array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/>
<array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/>
@ -2954,7 +2958,7 @@ to upconvert to 32b float internally?
<!-- 0x8e1d-0x8e1f invalid -->
<!-- 0x8e20-0x8e25 more perfcntr sel? -->
<!-- 0x8e26-0x8e27 invalid -->
<reg32 offset="0x8e28" name="RB_UNKNOWN_8E28" low="0" high="10"/>
<reg32 offset="0x8e28" name="RB_CMP_DBG_ECO_CNTL"/>
<!-- 0x8e29-0x8e2b invalid -->
<array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>
<array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/>
@ -4306,7 +4310,7 @@ to upconvert to 32b float internally?
<!-- always 0x100000 or 0x1000000? -->
<reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/>
<reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
<reg32 offset="0xb602" name="TPL1_UNKNOWN_B602" low="0" high="7" type="uint" usage="cmd"/>
<reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="cmd"/>
<reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL">
<bitfield name="MODE" pos="0" type="boolean"/>
<bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
@ -4978,6 +4982,11 @@ to upconvert to 32b float internally?
<reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
<reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
<reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/>
<reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-">
<bitfield pos="0" name="FASTBLEND" type="boolean"/>
<bitfield pos="1" name="LPAC" type="boolean"/>
<bitfield pos="2" name="RAYTRACING" type="boolean"/>
</reg32>
</domain>
</database>