fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-06 02:58:05 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

vc4: Make sure we don't overflow texture input/output FIFOs when threaded.

Browse source 
I dropped the first hunk of this change last minute when I decided it
wasn't actually needed, and apparently failed to piglit it in simulation.
The simulator threw an an assertion in gl-1.0-drawpixels-color-index,
which queued up 5 coordinates (3 before a switch, two after) before
loading the result.
This commit is contained in:
Eric Anholt 2016-11-22 13:31:46 -08:00
parent ea417f5335
commit ff018e0979
1 changed files with 3 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
src/gallium/drivers/vc4/vc4_qir_schedule.c
View file

@ -344,7 +344,7 @@ calculate_forward_deps(struct vc4_compile *c, void *mem_ctx,
* If the texture coordinate fifo is full, block this
* on the last QOP_TEX_RESULT.
*/
if (state.tfreq_count == 8) {
if (state.tfreq_count == (c->fs_threaded ? 4 : 8)) {
block_until_tex_result(&state, n);
}
@ -366,7 +366,8 @@ calculate_forward_deps(struct vc4_compile *c, void *mem_ctx,
*/
if (inst->op == QOP_TEX_S ||
inst->op == QOP_TEX_DIRECT) {
if (state.tfrcv_count == 4)
if (state.tfrcv_count ==
(c->fs_threaded ? 2 : 4))
block_until_tex_result(&state, n);
state.tfrcv_count++;
}