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intel/brw: Fix Xe2+ SWSB encoding/decoding for DPAS instructions

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SBID SET can only be used on SEND, SENDC, or DPAS instructions.  The
existing code was handling SET for SEND/SENDC, but was using the wrong
encoding for DPAS.  Add a new case to handle that and make it clear that
the existing code is only for SEND/SENDC.

While here, rewrite the encoder to use 2-bit binary immediates shifted
up into the mode [9:8] field, rather than pre-shifted hex values.  This
matches the documentation better and is a little easier to follow.

On the decode side, we were incorrectly decoding MATH instructions.
Because they're marked is_unordered, we were hitting the SEND/SENDC
decoding, which is incorrect for MATH.

Fixes 22 cooperative matrix tests on Lunar Lake.

Huge thanks to Paulo Zanoni for bisecting failures to one of my commits,
then analyzing shaders and experimenting to discover that the failure
was really an unrelated bug, just being provoked by different choices of
registers.  His work narrowing the problem down made it much easier to
discover and fix this bug.

Backport-to: 24.2
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30705>
(cherry picked from commit d22d6d814d)
This commit is contained in:
Kenneth Graunke 2024-08-16 13:01:44 -07:00 • committed by Eric Engestrom
parent 9bf42eeb30
commit feb9b69220
2 changed files with 30 additions and 10 deletions
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2
.pick_status.json
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@ -244,7 +244,7 @@
"description": "intel/brw: Fix Xe2+ SWSB encoding/decoding for DPAS instructions",
"nominated": true,
"nomination_type": 4,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

38
src/intel/compiler/brw_eu_defines.h
View file

@ -968,18 +968,27 @@ tgl_swsb_encode(const struct intel_device_info *devinfo,
} else if (swsb.regdist) {
if (devinfo->ver >= 20) {
if ((swsb.mode & TGL_SBID_SET)) {
unsigned mode = 0;
if (opcode == BRW_OPCODE_DPAS) {
mode = (swsb.mode & TGL_SBID_SET) ? 0b01 :
(swsb.mode & TGL_SBID_SRC) ? 0b10 :
/* swsb.mode & TGL_SBID_DST */ 0b11;
} else if (swsb.mode & TGL_SBID_SET) {
assert(opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC);
assert(swsb.pipe == TGL_PIPE_ALL ||
swsb.pipe == TGL_PIPE_INT || swsb.pipe == TGL_PIPE_FLOAT);
return (swsb.pipe == TGL_PIPE_INT ? 0x300 :
swsb.pipe == TGL_PIPE_FLOAT ? 0x200 : 0x100) |
swsb.regdist << 5 | swsb.sbid;
swsb.pipe == TGL_PIPE_INT ||
swsb.pipe == TGL_PIPE_FLOAT);
mode = swsb.pipe == TGL_PIPE_INT ? 0b11 :
swsb.pipe == TGL_PIPE_FLOAT ? 0b10 :
/* swsb.pipe == TGL_PIPE_ALL */ 0b01;
} else {
assert(!(swsb.mode & ~(TGL_SBID_DST | TGL_SBID_SRC)));
return (swsb.pipe == TGL_PIPE_ALL ? 0x300 :
swsb.mode == TGL_SBID_SRC ? 0x200 : 0x100) |
swsb.regdist << 5 | swsb.sbid;
mode = swsb.pipe == TGL_PIPE_ALL ? 0b11 :
swsb.mode == TGL_SBID_SRC ? 0b10 :
/* swsb.mode == TGL_SBID_DST */ 0b01;
}
return mode << 8 | swsb.regdist << 5 | swsb.sbid;
} else {
assert(!(swsb.sbid & ~0xfu));
return 0x80 | swsb.regdist << 4 | swsb.sbid;
@ -1007,7 +1016,8 @@ tgl_swsb_decode(const struct intel_device_info *devinfo,
{
if (devinfo->ver >= 20) {
if (x & 0x300) {
if (is_unordered) {
/* Mode isn't SingleInfo, there's a tuple */
if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC) {
const struct tgl_swsb swsb = {
(x & 0xe0u) >> 5,
((x & 0x300) == 0x300 ? TGL_PIPE_INT :
@ -1017,6 +1027,16 @@ tgl_swsb_decode(const struct intel_device_info *devinfo,
TGL_SBID_SET
};
return swsb;
} else if (opcode == BRW_OPCODE_DPAS) {
const struct tgl_swsb swsb = {
.regdist = (x & 0xe0u) >> 5,
.pipe = TGL_PIPE_NONE,
.sbid = x & 0x1fu,
.mode = (x & 0x300) == 0x300 ? TGL_SBID_DST :
(x & 0x300) == 0x200 ? TGL_SBID_SRC :
TGL_SBID_SET,
};
return swsb;
} else {
const struct tgl_swsb swsb = {
(x & 0xe0u) >> 5,