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radeon: add basic register setup for per-sample shading

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Only for Cayman, SI, CIK.
This commit is contained in:
Marek Olšák 2014-05-06 13:44:27 +02:00
parent 3aed75c859
commit fe98bfb261
4 changed files with 13 additions and 9 deletions
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6
src/gallium/drivers/r600/evergreen_state.c
View file

@ -1406,7 +1406,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
if (rctx->b.chip_class == EVERGREEN)
rctx->framebuffer.atom.num_dw += 14; /* Evergreen */
else
rctx->framebuffer.atom.num_dw += 25; /* Cayman */
rctx->framebuffer.atom.num_dw += 28; /* Cayman */
/* Colorbuffers. */
rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
@ -1679,7 +1679,7 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r
evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
} else {
cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples);
cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples, 1);
}
}
@ -2181,8 +2181,6 @@ void cayman_init_common_regs(struct r600_command_buffer *cb,
r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
r600_store_value(cb, 0);
r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));

7
src/gallium/drivers/radeon/cayman_msaa.c
View file

@ -191,6 +191,8 @@ void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
};
unsigned log_samples = util_logbase2(nr_samples);
unsigned log_ps_iter_samples =
util_logbase2(util_next_power_of_two(ps_iter_samples));
r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, S_028BDC_LAST_PIXEL(1) |
@ -201,11 +203,13 @@ void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
S_028804_PS_ITER_SAMPLES(log_samples) |
S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
r600_write_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1));
} else {
r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, S_028BDC_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
@ -214,5 +218,6 @@ void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
r600_write_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, 0);
}
}

3
src/gallium/drivers/radeon/r600d_common.h
View file

@ -160,6 +160,9 @@
#define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F)
#define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF
#define EG_R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C
#define EG_S_028A4C_PS_ITER_SAMPLE(x) (((x) & 0x1) << 16)
#define CM_R_028804_DB_EQAA 0x00028804
#define S_028804_MAX_ANCHOR_SAMPLES(x) (((x) & 0x7) << 0)
#define S_028804_PS_ITER_SAMPLES(x) (((x) & 0x7) << 4)

6
src/gallium/drivers/radeonsi/si_state.c
View file

@ -1921,7 +1921,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
sctx->framebuffer.atom.num_dw += state->zsbuf ? 23 : 4;
sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
sctx->framebuffer.atom.num_dw += 25; /* MSAA */
sctx->framebuffer.atom.num_dw += 28; /* MSAA */
sctx->framebuffer.atom.dirty = true;
}
@ -2026,7 +2026,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
cayman_emit_msaa_sample_locs(cs, sctx->framebuffer.nr_samples);
cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples);
cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples, 1);
}
/*
@ -3041,8 +3041,6 @@ void si_init_config(struct si_context *sctx)
si_cmd_context_control(pm4);
si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);