ac: Add rt_version

rt_version describes which generation of RT capabilities a chip has.
This matches what PAL does.

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34273>
This commit is contained in:
Konstantin Seurer 2025-04-08 23:10:56 +02:00 committed by Marge Bot
parent c33e598f39
commit fe739a2da2
3 changed files with 26 additions and 0 deletions

View file

@ -1719,6 +1719,13 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->has_image_bvh_intersect_ray = info->gfx_level >= GFX10_3 ||
info->family == CHIP_GFX1013;
if (info->gfx_level >= GFX12)
info->rt_ip_version = RT_3_1;
else if (info->gfx_level >= GFX11)
info->rt_ip_version = RT_2_0;
else if (info->has_image_bvh_intersect_ray)
info->rt_ip_version = RT_1_1;
set_custom_cu_en_mask(info);
const char *ib_filename = debug_get_option("AMD_PARSE_IB", NULL);

View file

@ -218,6 +218,7 @@ struct radeon_info {
enum vcn_version vcn_ip_version;
enum sdma_version sdma_ip_version;
enum rt_version rt_ip_version;
/* Kernel & winsys capabilities. */
uint32_t drm_major; /* version */

View file

@ -255,6 +255,24 @@ enum sdma_version {
SDMA_7_0 = SDMA_VERSION_VALUE(7, 0),
};
/* The enum values match PAL so they can be written into RRA files. */
enum rt_version {
RT_NONE = 0x0,
RT_1_0 = 0x1,
/* GFX10.3 */
RT_1_1 = 0x2,
/* GFX11 */
RT_2_0 = 0x3,
RT_3_0 = 0x4,
/* GFX12 */
RT_3_1 = 0x6,
};
const char *ac_get_family_name(enum radeon_family family);
enum amd_gfx_level ac_get_gfx_level(enum radeon_family family);
const char *ac_get_llvm_processor_name(enum radeon_family family);